Warpage Tuning Study for Multi-chip Last Fan Out Wafer Level Package

Transcription

1 2017 IEEE 67th Electronic Components and Technology Conference Warpage Tuning Study for Multi-chip Last Fan Out Wafer Level Package Hung-Yuan Li, Allen Chen, Sam Peng, George Pan, and Stephen Chen Siliconware Precision Industries Co., Ltd. No. 19, Keya Rd., Daya, Taichung, Taiwan, R.O.C. Abstract In recent years, the IoT popularity pushes the package development of 3C products into a more functional and thinner target. For high I/O density and low cost considered package, the promising Fan-out Wafer Level Packaging (FOWLP) provides a solution to match OSAT existing capability; besides, the chip last process in FOWLP can further enhance the total yield by selectable known-good dies (KGDs). However, under processing, the large portion of molding compound induces high warpage to challenge fabrication limitation. The additional leveling process is usually applied to lower the warpage that caused by the mismatch of coefficient of thermal expansion and Young s modulus from carriers, dies, and molding compound. This process results in the increase of package cost and even induce internal damages that affect device reliability. In order to avoid leveling process and improve warpage trend, in this paper, we simulated several models with different design of molding compound and dies, and then developed a multi-chip last FOWLP test vehicle by package dimension of 12x15 mm 2 with 8x9 and 4x9 mm 2 multiple dies, respectively. The test vehicle performed three redistribution layers (RDLs) including one fine pitch RDL of line width/line spacing 2um/2um, which is also the advantage of multi-chip last FOWLP, and also exhibited ball on trace structure for another low cost option. For the wafer warpage discussion, the results showed that tuning the thickness of molding compound can improve warpage trend, especially in the application of high modulus carrier, which improved wafer warpage within 1mm; for package warpage discussion, the thinner die can lower the warpage of package. Through well warpage controlling, the multi-chip last FOWLP package with ball on trace design was successfully presented in this paper, and also passed the package level reliability of TCB 1000 cycles, HTSL 1000 hrs, and uhast 96 hrs, and drop test by board level reliability. Keywords- FOWLP; Multi-Chips Module; Carrier; Fine Pitch RDL; Warpage; Molding Compound; Ball on Trace I. INTRODUCTION In recent years, the mobile devices inevitably push the package development into the complexity of functional integration such as multi-chips module (MCM) [1] or system in package (SiP) [2] which possesses a smaller form factor with good power efficiency, thermal dissipation, and electrical performance with a lower manufacturing cost. In order to accommodate the purpose of such high I/O density with low bump pitch, the 3D IC was demonstrated that logic IC utilized through silicon via (TSV) stacking high bandwidth memory on it; another solution is that 2.5D IC was also presented several years ago, which logic IC and high bandwidth memory were independent stacking on through silicon via (TSV) [3]. However, it s difficult for the business of mobile market because their applications are limited in high cost and complex functions design. For cost concerned in mobile market, the Fan-out Wafer Level Packaging (FOWLP) becomes a promising solution to mobile and IoT applications. Since the embedded fan-out patent [4], which was filed in 2001, and the technical paper [5] that was published in 2006 by Infineon [6], the FOWLP has been used in various products such as baseband, RF transceiver, and power management ICs by lots of companies such as Infineon, Intel, Marvell, Spreadtrum, Samsung, LG, Huawei, Motorola, and Nokia, among others. In the next few years, many outsourced semiconductor assembly and test services (OSATS) and foundries are developing their own FOWLP for the forecasted explosive growth of this market [7]. Basically, John H. Lau well defined two methods to build the FOWLP. One is chip-first and the other one is chip-last. For the chip-first method shown in Figure 1, the device wafer is tested for known-good dies (KGDs) and then singulated into individual dies. This is followed by picking up the KGDs and placing them on a temporary carrier. If KGDs face down, the reconfigured carrier is then overmolded before removing the carrier and the doublesided tape and turning the whole molding around; if KGDs face up, no need to remove the carrier and the double-sided tape. Next comes building the RDLs and pads. Finally, solder balls are mounted and the whole molding is diced into individual packages. For the chip-last method which this paper discusses, the process flow is shown in Figure 2. It is so different that all processes only work on a wafer carrier. After KGDs complete, they are picked up on the contact pad. Next comes over molding the whole reconfigured carrier with molding compound. Then, backgrind the over mold, attach to a second carrier, and then remove the first carrier. Finally, the solder balls are mounted on the bottom RDL and the molded wafer is diced into individual packages [7]. Comparing to chip-first FOWLP, the molding is the last process, which can protect chips on multiple RDLs, therefore it can eliminate die shift issue during RDL fabrication, and allows the fabrication fine pitch RDL on carrier wafer for high-end applications [8] /17 $ IEEE DOI /ECTC

2 (a) Figure 2. The process flow of chip-last FOWLP (b) Figure 1. Two process flow of chip-first FOWLP: (a) KGDs face down; (b) KGDs face up Although chip-last FOWLP performs lots of advantages, there are numerous processing paths needed to be checked out. The most inevitable challenge was wafer warpage control. The warpage is the composite behavior from thermal and mechanical properties of diverse materials. Since warpage increase is natural to film stacking structure, it s affected not only by multiple thermal treatments but also by residual stress induced by material itself. The terms of warpage used in this paper is defined as smiling or positive value where wafer curve is concave behavior, and is defined as crying or negative value where wafer curve is convex behavior [7]. In this paper, we focus on warpage tuning study to multi-chip last FOWLP. As previous researches [9-11], the material compositions and process flows resulted in warpage deviation that affected the package yield and process cost. Therefore, the thickness of molding compound, type of molding compound, and the thickness of top die are selected as the optimized factors that dominate the warpage trend. And then, a test vehicle based on simulation results will be presented and discussed within diverse carriers. For ball on trace structure study shown in Figure3, the cost effective RDL based on WLCSP options are discussed previously [12], which meet the board level reliability by drop and thermal cycling requirements for most WLCSP applications. Unlike standard WLCSP, the ball on trace structure eliminates one mask stack-up, so it can provide cost and cycle time savings. In this paper, the multi-chip last FOWLP with ball on trace structure was also demonstrated through package and board level reliability. Figure 3. Ball on trace structure applied in the multi-chip last FOWLP 1385

3 II. TEST VEHICLE DEMONSTRATION 2.1 Package Design For development of a multi-chip last FOWLP, the package size of 15 x 12 mm 2 was designed shown in Figure 4. Through the daisy chains of three RDLs, around 1000 I/Os connected to two chips of 9 x 8 and 9 x 4 mm 2 which minimum bump pitch was 40 um. And the BGA ball pitch of package was 400 um. The three RDLs included one fine pitch RDL of line width/line spacing 2um/2um, which were also designed the pattern of 2um/3um and 2um/5um for photolithography testing. The minimum pitches of the other two RDLs were 5um/5um and 10um/10um, respectively. Besides, the ball on trace structure was also applied to validate in this test vehicle. The ball on trace structure just skipped UBM layer and utilized ball directly standing on RDL. The design was depended on WLCSP design rules as reference. Figure 4. Schematic of Multi-chip last FOWLP layout For reliability validation of multi-chip last FOWLP, the daisy chains design shows in Figure 5. The evaluation purpose was to pass package level and board level reliability defined from JEDEC. The reliability analysis involve DIE1- to-die2 continuity, chains to chains leakage, bump continuity, BGA ball continuity through RDLs, BGA ball continuity through PCB, and corner BGA ball continuity. Each abnormal resistance deviation was analyzed by nondestructive and destructive methods, and it will be discuss in the following section. Figure 5. Daisy chains design for reliability analysis 2.2 Process Flow The detailed process flow of this test vehicle is the same with Figure 2. At first, the carrier preparation was to implement glass as carrier which needed to coat release layer for future de-bonding process. The characteristics of carrier such as CTE and thickness took an important role to tune warpage trend. Then, a release layer was coated on glass carrier, which thickness and composition not only affected the yield of de-bonding process also probably induced laser residue on RDL after de-bonding. Therefore, the release layer of multi-chip last FOWLP must be optimized to withstand three RDLs process without any side effective issues. After carrier preparation, the three RDLs and several passivations were patterned layer by layer, which LW/LS were 10um/10um, 5um/5um, and 2um/2um, sequentially. These multiple RDLs were formed by electroplating Cu to achieve layer-to layer interconnection from bottom to top. At last, the micro pads were patterned on the top of fine pitch RDL for interconnection between DIE1 and DIE2. The above procedures were also called RDL first FOWLP, because the RDLs were fabricated first, and then the known-good RDLs defined on carrier were selected to bond DIE1 and DIE2. The molding compound in the wafer form was following to fill with whole dies by indicated thickness and type which referred to simulation results. At this stage, the warpage trend reversed to serious crying curve due to high modulus molding compound, so in this paper the stiffer first carrier was applied to strength the wafer for next carrier bonding process. Then, the second selective glass carrier bonded to molding compound surface for the following first carrier de-bonding process. The warpage became more smiling when second glass carrier bonding; then the first carrier was removed by laser releasing process. In this process, laser scanned on glass carrier to dissociate release layer, and cleaning process was implemented to the surface for the following backside process. For BGA ball placement, we studied in ball on trace structure which skipped UBM process shown in Figure 3. This ball on trace structure eliminated one passivation which contributed high warpage to ball placement process. The high warpage may cause problems of ball spilling or missing ball. Finally, the multi-chip last FOWLP was established and moved to JEDEC component level reliability tests. 2.3 Reliability Test After die singulation, the package was delivered to package level reliability (PLR) tests which were validated by three different categories of test condition, including Temperature Cycling Test (TCT), Temperature Humidity Test (THT), and Unbiased Highly Accelerated Stress Test (uhast). Before TCT and THT, an additional preconditioning test was implemented to quickly validate device performance and identify advance failure in early stage. Preconditioning test consisted of baking, soaking based on Moisture Level 3 (MSL3), and three times of 1386

4 reflow process. All the detailed PLR conditions and checkpoints are listed in TABLE 1. For each checkpoint, standard open and short tests measured actual resistance value throughout interconnection chains discussed in section 2.1 for all RDLs. The criteria for passed units were limited to resistance change smaller than 10%. For board level reliability (BLR), through surface mount technology (SMT), the daisy chains on printed circuit board (PCB) were also designed for bump check of BGA corner and micro-bumps. The detailed BLR conditions and checkpoints are also listed in TABLE 1. The failure criteria was the first indication of resistance value of 1000 followed by 3 additional such indications during 5 subsequent drops. The detailed discussion of PLR and BLR results to the multi-chip last FOWLP will be presented in the following section. TABLE 1. The conditions and checkpoints for PLR and BLR III. RESULT AND DISCUSSION 3.1 Warpage optimization In order to avoid leveling process, the multi-chip last FOWLP needed to be optimized each material characteristic that induced warpage deviation in this test vehicle. The thickness of molding compound and dies were selected to improve warpage trend during processing. The characteristics of silicon, glass, two kinds of molding compound, and passivation shown in TABLE 2 were applied to build the model of package form and wafer form, respectively. By the ANSYS of finite element method (FEM) software, the models were divided to quarter setup for simulating the warpage trend at room and high temperature. For molding compound selection, since the thickness of RDLs were just only several micrometers, the total package thickness depended on molding compound, even for exposure die package. Besides, the CTE of molding compound also dominated warpage trend during molding compound curing process. Therefore, selective thickness and type of molding compound were designed from leg 2 to leg 4 shown in TABLE 3 for warpage comparison. Additionally, under modification of molding compound thickness, the die thickness was also considered to be a key factor for warpage tuning as leg 1 shown in TABLE 3. TABLE 2. Material characteristics Material Silicon Glass MC-A MC-B Passivation Modulus (GPa) CTE1 (ppm) CTE2 (ppm) Tg () TABLE 3. Leg compositions of molding compound and die Leg Molding Compound Thickness (um) Molding Compound Type A A A B Die Thickness (um) The calculation result of package form is shown in Figure 6. The warpage curve will affect stand-off-height after SMT. By factor comparison, die thickness and molding compound type were not key factors to warpage curve, but molding compound thickness played an important role to tune package warpage. The warpage deviation of leg 1 and leg 2 were so high that may cause stress defects by SMT process, especially in the corner of package. However, leg 3 and leg 4 show better warpage trends at room and high temperature, because the molding compound thickness of leg 3 and leg4 are lower, which also exhibited thin package with thin dies. By the way, as well as molding compound was thin enough, the type of molding compound affected the package warpage little. Figure 6. Package warpage comparison by calculation Actually, the FOWLP usually suffers warpage issue in wafer form which leads not to process in limited equipment. Even more, at some stages, the wafer is acceptable to track in the equipment, but unable to track out the equipment due to high warpage deviation during processing. In this paper, the multi-chip last FOWLP were capable of completion all process, and tried to skip leveling by optimized material compositions. Therefore, by wafer form calculation shown in Figure 7, the leg 4 showed worse wafer warpage than leg 3, which was affected by low CTE molding compound. The 1387

5 reason was that higher CTE molding compound could balance the warpage, because from this sandwich structure, the dies were in the middle layer between two high CTE materials: glass carrier and molding compound. The effect of molding compound type is shown in leg 3 which performed the best warpage result in wafer form at room temperature. Secondly, comparing to leg 1, the leg 2 showed worse wafer warpage because much volume of molding compound tuned the warpage more crying through molding compound curing process. From Figure 6 and Figure 7, the warpage results provided a relative trend for us to realize the effect in certain package design. For the compositions of multi-chip last FOWLP, the leg 3 was selected as our best known condition for the realistic layout of test vehicle. Figure 7. Wafer warpage comparison by calculation 3.2 Experimental Result From calculation results, the test vehicle of multi-chip last FOWLP was produced by the package dimension of 12x15x0.6 mm 3 which included 8x9 mm 2 and 4x9 mm 2 multiple dies. Through calculated results of 300um thickness of molding compound and 200um thickness of die, the standard glass carrier was applied to fabricate several processes of three RDLs, micro pads, molding compound including die bonding, second carrier bonding, and first carrier debonding, which are shown in figure 2. The RDL3 was demonstrated the specific design 2um/2um of fine line width/line spacing shown in figure 8, which were located on the interconnection between DIE1 to DIE2. For avoidance of stress concentration in RDL trace neck, the shape of RDL pad was designed as a drop which involved obtuse pad for stress release. For well warpage controlling through processes, the warpage of each process was measured after process completion shown in Figure 9. For warpage contribution of RDLs, the passivation usually results in high warpage deviation. However, in packaging industry, the passivation provides the benefits of great electrical insulation and RDL compatibility, especially in stress buffering which generates from temperature cycling test and mechanical shock applied in mobiles devices and temperature-sensitive components [13]. In this study, the specific passivation possessed high CTE and low modulus relatively comparing to other materials, even the 60ppm of low CTE passivation shown in TABLE 2 was applied. About the effect of Tg, the low Tg passivation generally produces low residual stress regarding to warpage reduction. Usually, in package technology development process, materials should be determined in advance prior to process window validation, and parameter optimization can be implemented. Thus, after glass carrier and passivation material were both decided, the layer number effect of RDLs could be taken into consideration. It is shown in Figure 9, which wafer warpage showed obvious increase with added RDLs. It indicated that warpage increased greatly after passivation patterning process, no matter what the types of glass carrier were. The trend correlated to the curing process after passivation patterning, because the tensile strength and residual stress of passivation increased depending on the curing temperature which generates stress within the material. With more passivation layers patterned on the glass carrier, the warpage was higher. For this test vehicle, three RDLs were general design in foundry interconnection manufacturing, so the same numbers of passivation layers were also applied. The characterization of warpage not only demonstrated warpage increase amount per layer, but also performed the effect of different types of carrier. Figure 9. Warpage comparison of different carrier Figure 8. Fine pitch of LW/LS 2um/2um For 800um thickness of glass carrier shown in Figure 9, the warpage gradient increased under RDLs and micro pad fabrication. It was the baseline for carrier type comparison. After molding compound process which included die bonding, the warpage declined to negative 1388

6 value which showed convex curve. The result had a little gap to calculated value -1000um shown in Figure 7. The reason probably indicated that each passivation suffered different curing times in the realistic process. With more curing processes, more long chain polymer complex can be generated to the branching and potential crosslinking [14], which induces the tensile strength and residual stress within the material. Furthermore, the first passivation covering on RDL1 through three times high temperature curing may perform different stress behavior by fully curing ratio, but the other passivations may resulted in different curing ratio. After second carrier bonding, the warpage became extremely increasing to positive value. The second glass carrier attached glue on molding compound to constrain the package as concave curve. And then, the release layer on first glass carrier was scanned by laser for debonding. When the first glass carrier released the wafer, the warpage declined to the value which was closed to the value of molding compound; the opposite symbols just meant different perspectives. In order to improve warpage trend during RDLs processes, 1000um thickness of glass carrier and 800um thickness of silicon carrier were applied to tune processing warpage. The warpage results from Figure 9 showed just little improvement by 1000um glass carrier. When layer by layer stacking, the thickness effect of 1000um glass carrier became ignorable. However, for the warpage limitation to equipments, the 1000um glass carrier even had contributed 200um thickness to warpage value. Comparing to the warpage trend of 800um silicon carrier, the warpage trend always maintained concave curve and was obviously improved during processing. This wafer form carrier was not only acceptable to all wafer level equipment, but provides around 38% warpage improvements. In addition, the processes of applied 800um silicon carrier were similar with glass carrier except for carrier debonding process. The release layer on transparent glass carrier was scanned and decomposed in original debonding process. In the silicon carrier process, there was no release layer on carrier, so no laser debonding process existed. The method to remove silicon carrier was to utilize mechanical polishing and chemical etching in the debonding process. The warpage results of second carrier bonding and carrier debonding will be discussed in the future. From experimental results, the characteristics of carrier dominated the warpage behavior through RDLs processing. There was no obvious warpage improvement by application of 1000um glass carrier; however, the 800um silicon carrier contributed lots of benefits not only to warpage tuning but also create another process flow for cost-down purpose. To develop new carrier to multi-chip last FOWLP needs to analyze the mechanism which affects the warpage trend. A general solution to thermal stresses of bi-layer bonding was from G. Stoney published in And then, for die to substrate assembly, The Suhir in the 1980 s revised several results in its die attaching and peeling solution. And then, for design purpose, M. Y. Tsai proposed accurate prediction for engineering application [15], which can instantly indicated key factor affected to stresses and deformations of assembly. In Stoney equation [16], we assume there was biaxial stress in thin film on thick carrier. No stress occurred in direction normal to substrate, and it was assumed isotropic film. The following modified equation shows the radius of curvature (r), the thickness of films (h), coefficient of thermal expansion (), temperature variation (T), and Young s modulus (E). The warpage can be transferred by the radius shown in Equation (1). For theoretical analysis, we assume each stage has two biaxial layers, which can be applied to evaluate the warpage caused by internal stress [17]. From the equation, the effect of carrier warpage depended on the carrier thickness of third power, but the effect of carrier warpage depended on the Young s modulus of one power, which meant the carrier thickness decides the warpage behavior when the delta CTE was fixed. When applying to our test vehicle which characteristics of glass and silicon carrier are shown in TABLE 2, the 1000um glass carrier which possessed the same CTE provides around 95% contribution to warpage tuning. But for theoretical calculation of 800um silicon carrier which possessed much higher modulus than glass carrier, the warpage could decline around 153% comparing to 800um glass carrier, even not included smaller delta CTE which silicon carrier assisted. Therefore, the silicon carrier performed more effective warpage tuning for our multi-chip last FOWLP. 3.3 Reliability Test Result For package level reliability, the whole package in sequence passed the required MSL3 with 260 precondition followed by TCB 1000 cycles, uhast 96 hrs, and HTSL 1000 hrs. And then the electrical resistance values were measured from the specific designed daisy chains. The all units passed the criteria limited to resistance change smaller than 10%, especially in that ball on trace structure was also validated. For board level reliability, the test pads of PCB for each package are shown in Figure 10. The packages were successfully mounted on the dimension of 132x77x1 mm 3 PCB through SMT shown in Figure 11 regarding to the JEDEC regulations [18]. After SMT, from x-ray inspection shown in Figure 12, there was no obvious abnormality on ball shape. For drop test result, all packages passed with under 30 cycles testing. Beyond 30 cycles by drop test, the first failure chain was found and performed high resistance change in the package corner. In the most packages through drop test, the first failed chain is generally located on the corners, because the internal stress resulted from thermal cycling or external stress resulted from drop impact, always produces on material diverged location corners. The Figure 13 shows that the corner ball was found intermediate metal compound (IMC) cracked between RDL and solder. (1) 1389

7 From previous paper review [19], the ball on trace structure which lacks of UBM needs to increase the thickness of RDL for IMC consumption. In this test vehicle, the thickness of RDL was indeed enhanced above 5um, so the failure mode matched previous experience. Furthermore, it was the first ball on trace structure that demonstrated in multi-chip last FOWLP. Figure 10. Test pads design on PCB (a) Figure 11. SMT results (a) Plane view; (b) Cross-section view (b) IV. CONCLUSION AND FUTURE WORK In this paper, a multi-chip last FOWLP was demonstrated by the package size of 15 x 12 mm 2 through the fabrication with the fine LW/LS 2um/2um of multiple RDLs and ~1000 I/Os connection. From simulation results, the optimized composites are thin molding compound and thin top die which are not only applied to package form but also to wafer form. And then the test vehicle showed warpage trend from release layer coating, three RDLs, die bonding, molding compound, to second carrier bonding, respectively. From the experimental results, the silicon carrier can significantly improve wafer warpage due to its high modulus from theoretical discussion. The test vehicle passed package level reliability of TCB 1000 cycles, HTSL 1000 hrs, and uhast 96 hrs, and also passed board level reliability, even it suffered IMC cracking in the corner beyond 30 cycle s examination. From warpage result of silicon carrier, the warpage was well controlled after molding compound; however, the second carrier needed to be selected to avoid warpage out of controlling. Whether the first carrier is glass or silicon, the characteristics of second carrier is another factor for warpage tuning, even though we suppose to advancedly modify molding compound instead of second carrier. The target is to skip second bonding for multi-chip last FOWLP. Besides, from cross-section image of package on PCB shown in Figure 14, the package warpage is obviously crying on PCB. Referring to leg 2 in Figure 6, we believe the thickness of top die should be lower when package dimension is fixed. After all, we demonstrate the multi-chip last FOWLP through a warpage tuning study, and also needs more material modification tasks in the future. Figure 14. Cross-section image shows the convex package bonding on PCB Figure 12. X-ray inspection shows no abnormality Figure 13. Cracked IMC was found by drop test REFERENCES [1] S. F. Al-sarawi, D. Abbott, P. D. Franzon A review of 3-D packaging technology, IEEE Trans. Compon. Packag. Manuf. Technol., vol. 21, pp. 2-14, Feb [2] M. Koyanagi, T. Fukushima, T. Tanaka, High-density through silicon vias for 3-D LSIs, Proc. IEEE., vol. 97, pp , Jan [3] Scott Chen, Simon Wang, John Hunt, William Chen, Leander Liang, Golden Kao, and Abner Peng, A Comparative study of a Fan Out Packaged Product : Chip First and Chip Last, 2016 IEEE 66th Electronic Components and Technology Conference, pp [4] H. Hedler, T. Meyer, B. Vasquez, Transfer wafer-level packaging, US Patent 6,727,576, filed on Oct. 31, 2001; patented on April 27, [5] M. Brunnbauer, E. Fürgut, G. Beer, T. Meyer, H. Hedler, J. Belonio, et al., An embedded device technology based on a molded reconfigured wafer, Proc. of ECTC, 2006, pp [6] J. Lau, Patents issues for fan-out wafer/panel packaging, Chip Scale Review, Nov/Dec 2015, pp [7] John H. Lau, Nelson Fan, Li Ming, Design, material, process, and equipment of embedded fan-out wafer/panel-level packaging, Chip 1390

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