The 2005 ITRS Assembly and Packaging Roadmap

Transcription

1 The 05 ITRS Assembly and Packaging Roadmap About ITRS ITRS = International Technology Roadmap for Semiconductors Combined effort by semiconductor industries worldwide Major revisions in odd numbered years with updates in even numbered years 05 revision published in December 05 Assembly and Packaging (A&P) is one of 14 chapters url: Page 1

2 ITRS A&P Chapter Organization Scope Difficult Challenges Technical Requirements Infrastructure Challenges Potential Solutions Tables Assembly and Packaging Roadmap Participants 05 W. R. Bottoms Chair William Chen Co-Chair Rongshen Lee Masanao Yano Michitaka Kimura Shoji Uegaki Abhay Maheshwari Shyi-Ching Liau Ralf Plieninger Henry Utsunomiya Debendra Mallik Chi-Shih Chang Voya Markovich Bob Pfahl Lei Mercado Joe Adam Zhiping Yang. John T. Fisher Stan Mihelcic George Harman Carl Chen Mahadevan K. Iyer Keith Newman Sergio Camelo Mike Hung Shuya Haruguchi Luu Nguyen Hirofumi Nakajima Ryo Haruta Kazuo Nishiyama Gilles Poupon Fumihiko Hayano Hajime Tomokage Hisao Kasuga Klaus Pressel Nobuo Futawatari Shigeru Utsumi Eiji Yoshida Bernd Roemer Takashi Takata Akira Yoshida Max Juergen Wolf Coen Tak Shigeki Ueda Page 2

3 Assembly and Packaging Roadmap 05 Packaging has become the limiting element in system cost and performance The Assembly and packaging role is expanding to include system level integration functions. As traditional Moore s law scaling become more difficult innovation in assembly and packaging innovation can take up the slack. The Consumerization of Electronics has arrived Golfball with Wireless Sensor Node and there are many implications Page 3

4 Computing System performance increase continues Example: Game Console from this Mini Football video game Circa: 1990s to this Page 4

5 Consumer Market Imperatives. Size Cost Functionality & Reliability Weight Power Assembly and Packaging Emerging as Limiting Factor for Cost and Performance Consumers now drive more than half of integrated circuit revenue Assembly and Packaging technology is a primary differentiator for consumer electronics These factors are driving an unprecedented pace of innovation in: New materials New Technologies New Systems integration Page 5

6 What s New for 05 Expanded Coverage System in Package Wafer level packaging Materials New Technologies Wafer thinning 3D Packaging and Systems Integration Embedded and integrated components Infrastructure Flexible packaging Medical and Biochip Packaging What s New for Continued New Tables Package Substrate Physical Properties Medical and Biochips Package Substrate Design Parameters Package Level System Integration Processes used for SiP System-in-a-Package Requirements Thinned Silicon Wafer Thickness 0mm/300mm Major Revisions to Existing Tables Die size Pin count Junction temperature Page 6

7 New Materials Cu interconnect Ultra Low k dielectrics High k dielectrics Organic semiconductors Green Materials Pb free Halogen free other New Packaging Technologies Thinned wafers 3D systems integration Wafer level packaging Bio-chips Integrated optics Embedded/integrated active and passive devices MEMS Printable circuits Semiconductors Light emitters RF Interconnect Flexible (wearable) electronics Page 7

8 Thinned Wafers/Die (a) Rolled Wafer 10µm m Thickness Wafer (b) Light Transparency Source: Shinko Electric Industry, Printable Electronics Inter-chip wiring by ink jet printing LED wiring by ink jet printing Source: SiP Consortium Page 8

9 System Integration System on Chip Cost / function Time to market MEMS Bio-Interface SiP and 3D Packaging Power supply System complexity Source: Fraunhofer IZM SiP in the Cellular Phone Source: T. Sakurai, University of Tokyo Page 9

10 Systems Integration in the Cellular Phone It is not only integrated circuits LCD Circuit Larger display, Color display Lower power consumption Higher resolution DSP CPU BB Dual CPU: Transmission /Application Tx Rx Circuit Smaller & lower power consumption of analog circuit Decrease of # of mounted components Embedded Antenna Smaller Stability of signal Influence on the human body Power Supply Circuit Smaller Size Camera Circuit Smaller Lower power consumption One unit of lens and control circuit Memory Circuit Memory area for downloaded software Higher memory capacity Plug In Memory Card Smaller, thinner Higher memory capacity Outer Interface Circuit Bluetooth, USB interface MP3, GPS interface Memory Card interface Source: H.Ueda JEITA Categories of SiP Horizontal Placement Wire Bonding Type Flip Chip Type Stacked Structure Interposer Type Wire Bonding Type Wire Bonding + Flip Chip Type Flip Chip Type Interposer-less Type Terminal Through Via Type Embedded Structure Chip (WLP) Embedded + Chip on Surface Type 3D Chip Embedded Type WLP Embedded + Chip on Surface Type Source: K. Nishi, Hitachi, JEITA, Revised by H. Utsunomiya Page 10

11 SiP- Multi level system Integration system partitioning in sub-system packages (SiP s) stackable thin packages containing passives and active chips testability of each package before stacking complete systems or sub-systems containing functional layers with embedded components Source: Fraunhofer IZM Realization of a Stackable Chip Package build-up layer Chip in Polymer filled through hole embedded chip and via to chip pad via to board metallization Cross section of a single stack package solder ball 0.5mm FR4 board Stack of 4 single packages Source: Fraunhofer IZM Page 11

12 Difficult Challenges Near Term Design tools and simulators for chip, package and substrate co-design Impact of new materials Package substrate requirements Embedded components Wafer Level Packaging Thinned die packaging High current density packages Flexible system Packaging 3D Packaging Fine Pitch Packages ITRS Power dissipation trends POWER (Watts) High Performance Cost-Performance With increased awareness, power increases are at at a slower rate Source : 05 ITRS Page 12

13 Difficult Challenges Long Term Package cost not scaling with die cost Small Die with High Pad Count and/or High Power Density High frequency die Emerging Device Types (Organic, Nanostructures, Biological) that require New Packaging Technologies System-level Design Capabilityfor Integrated Chips, Passives, and Substrates Address the Total System Silicon Packages Heat Sinks Architectural improvements in Silicon process & design Enhance Heat Spreading (Package) Increase Power handling (Heatsinks) Expand System Thermal Envelopes & optimize thermals Facilities Systems Page 13

14 Some requirements have no known solution Year of Production Performance: Chip-to-Board for Peripheral Buses (MHz) [7] Logic/memory 125/ / /10 150/10 150/10 150/10 150/10 Cost-performance (for multi-drop nets) High-performance (for differentialpair point-to-point nets) Harsh Some requirements have no known solution Year of Production Dielectric Loss (at 1 GHz) Rigid Structure Buildup Tape Structure Ceramics Structure Page 14

15 Some requirements have no known solution Year of Production Low cost/handheld (# die / stack) High performance (# die / stack) Low cost/handheld (# die / SiP) High performance (# die / SiP) Minimum component size (microns) 0x100 0x100 0x10 0 0x100 0x100 0x100 0x100 Some requirements have potential solutions identified but not proven Year of Production Wire bond pitch single in-line (micron) 2-row staggered pitch (micron) Three tier pitch pitch (micron) Wire bond wedge pitch (micron) Flying lead pitch (micron) Flip chip area array pitch (micron) Page 15

16 Conclusions Scaling for conventional planar ICs is nearing its practical limits Assembly and packaging is bridging the gap by enabling economic use of the 3 rd dimension System level integration is emerging as a driver of assembly and packaging solutions replacing single chip packaging A majority of materials used in packages in 03 will be replaced before the end of this decade. Improved tools for co-design and simulation will be necessary to meet Roadmap requirements Cost is the greatest challenge for assembly and packaging Thank You! Page 16