Lecture 3 HETEROGENEOUS SYSTEMS

Transcription

1 Lecture 3 HETEROGENEOUS SYSTEMS

2 Why heterogeneous systems Increasing development costs / node Cost/gate has stalled Diminishing margins for conventional chips Heterogeneous systems A chip having more than one purpose/material/application Performance and power gains Added value New applications: Low-power IoT, quantum, sensing... Mattias Borg / More than Moore Future of Electronics 1

3 Outline 3D integrated circuits Monolithic (III-V) integration Mattias Borg / More than Moore Future of Electronics 2

4 3D circuits Achieves a highly integrated system, by vertically stacking and connecting various materials, technologies and functional components together. Multifunctionality (union of various circuit types) Increased performance Shorter interconnects Memory on-chip and close by Reduced power consumption Small form factor and packaging Increased yield Two main types: System-in-Package & System-on-Chip Mattias Borg / More than Moore Future of Electronics 3

5 3D strategies I System-in-Package (SiP) Test chips and pick-and-place the working ones to stack Known-Good-Die High yield, flexibility in choice Chips connected via bond wires and solder bumps. Low throughput and testing is expensive Successful SiP example: MEMS sensors in cell phones Accelerometer Gyroscope Microphone iphone 4 MEMS gyroscope Mattias Borg / More than Moore Future of Electronics 4

6 3D strategies II - System-on-Chip Flip-chip bonding Or Direct Wafer bonding Through-Si-Vias (TSV) to connect chips Via-first or Via-last Closer integration than SiP Interconnections can occur at a lower level. > 10 6 TSV connections... Mattias Borg / More than Moore Future of Electronics 5

7 Example - 3D Memory/IC Integrate CPU caches (SRAM/eDRAM) or even main memory (DRAM) on second chip level Bandwidth between main mem and CPU improves dramatically Not pin-limited! On-chip buses fetch s of bits at once 12.8 GB/s 128 GB/s (IBM 3D DDR3 2011) Much reduced interconnect distance (less delay/bit-operation) Less area cost on CPU chip (High density) DRAM stack Logic CMOS Mattias Borg / More than Moore Future of Electronics 6

8 Typical SoC 3D circuit process Surface planarisation (CMP) Thinning of wafers Bonding/Alignment TSV formation Mattias Borg / More than Moore Future of Electronics 7

9 Planarisation Chemical Mechanical Polishing Has become one of the most important tools in semiconductor industry Enables high-precision planarisation of wafers/deposited films. Up to nanometer thickness precision Cu, Al, SiO 2, Si 3 N 4, W, etc. Process needs calibration for each material w/o CMP with CMP Mattias Borg / More than Moore Future of Electronics 8

10 Direct Bonding The joining of two surfaces and subsequent merging into one unit Chip-2-chip Chip-2-wafer Wafer-2-Wafer Prepare surfaces Put surfaces together Anneal to increase bonding strength Good bonding strength = 1-2 J/cm 2 Mattias Borg / More than Moore Future of Electronics 9

11 Types of bonding Polymer adhesive (BCB, SU8) Low temperature, accuracy (~2 µm) Si/SiO 2 direct bonding Van der Waals/H bonds Covalent bonds when annealed - High temperature needed (>800 C) Metallic/eutectic Metal diffusion Eutectic alloy lower temperature Cu-Sn, Au-Si,... Mattias Borg / More than Moore Future of Electronics 10

12 Maszara Blade Method Push blade of known thickness inbetween bonded wafers Length of unbonded area gives bonding strength G = 3 16 Et 3 y 2 L 4 [J/m 2 ] E = Young s modulus L = Length of crack y = load-point displacement t = wafer thickness Mattias Borg / More than Moore Future of Electronics 11

13 Particle defects Single Particles give rise to extended bonding defects Large defects compared to particle size r = 2E t w 3 3γ 1 4 h 1 2 Particle size Yokoyama Semicond. Sci. Techn Gueguen et al. Microelectr. Eng Mattias Borg / More than Moore Future of Electronics 12

14 Summary 3D stacked circuits Benefits: SiP: Straight-forward combination of chip types SoC: Larger bandwidth, lower power Allows for wide range of chip combinations Separately optimizable chip layers Known Good Die high yield Drawbacks: Low through-put Cost is high Alignment accuracy limit (max TSV spacing) Next step: Monolithic integration Higher throughput Perfect alignment Connection density like 2D Mattias Borg / More than Moore Future of Electronics 13

15 Monolithic 3D circuits Second layer of logic devices on top of base layer Allows for same connection density as 2D Thermal budget of second device layer is too high (1000 C) LETI used solid state epitaxy to recrystallize doped amorphous Si at 600 C Alternative to standard node scaling..? LETI IEDM 2011 Mattias Borg / More than Moore Future of Electronics 14

16 III-V materials integration III-V semiconductors promising for Logic & communication, Photonics quantum technology Examples: GaAs, InAs, In x Ga 1-x As, GaSb, InSb, GaN, In x Ga 1-x N,... Why integrate them? In and Ga are rare on Earth Substrates are frail and VERY expensive Si technology is great, why not use III-V to extend it? Mattias Borg / More than Moore Future of Electronics 15

17 Monolithic III-V 3D integration Yokoyama et al. SST 2013 Czornomaz et al IEDM 2013 Mattias Borg / More than Moore Future of Electronics 16

18 III-V integration by epitaxy Epitaxy: Crystal growth on a substrate crystal Takes on the same lattice orientation as substrate Single crystals are possible Best material quality MOVPE: Growth from a vapor High through-put Uses safe metalorganic molecules as precursors Standard method for III-V based LED fabrication Epitaxy (MOVPE) TMIn TBAs Surface diffusion Crystalline substrate Typical Temperature: ºC Mattias Borg / More than Moore Future of Electronics 17

19 Challenge 1 - Lattice-mismatch Epi material f = a e a s a s Substrate Pseudo-morphic heterostructure Strain energy builds up with increased thickness Mattias Borg / More than Moore Future of Electronics 18

20 Strain relaxation Misfit dislocation Pseudo-morphic heterostructure Relaxed heterostructre Increasing lattice mismatch < 2% 2% 4% > 5% Mattias Borg / More than Moore Future of Electronics 19

21 How thick can you grow? h = layer thickness E strain h Not stable when E strain > critical thickness, h c Matthews-Blakeslee model ν = Poisson ratio ε 0 = lattice mismatch b = slip distance (Burgers vector) a = bulk lattice constant of film Mattias Borg / More than Moore Future of Electronics 20

22 Challenge 2 - Crystal structure mismatch Si III-V Diamond structure Two interlaced face-centered cubic (fcc) lattices The second lattice is translated a/4*(1,1,1) Zinc-blende structure Same structure as diamond but one fcc lattice has group III and the second one has group V species Mattias Borg / More than Moore Future of Electronics 21

23 Anti-phase boundary defects Very detrimental defect due to highly polarised defect states. Anti-phase boundary DF-TEM of CuAlNi shape-memory alloy Mattias Borg / More than Moore Future of Electronics 22

24 Julian et al JCG 2014 Strategies - Buffer layers Idea: Reduction of defects in top layer by containing defects in a thick buffer layer. Why? Dislocations can terminate when merging Device layer InP Si Mattias Borg / More than Moore Future of Electronics 23

25 Buffer layer optimization Off-cut substrates Graded buffers Superlattices Maximizes nucleation density Fischer et al. JAP 1986 Grassman et al. TED 2010 Nikishin et al. APL 1999 Mattias Borg / More than Moore Future of Electronics 24

26 Strategies - Epitaxial Lateral Overgrowth Growth through small trench Filters out defects Layer on top of mask is highquality Problem with void formation upon merging stripes Still high defect density above openings Wierzbicka et al. JAP 2009 Mattias Borg / More than Moore Future of Electronics 25

27 Strategies - Aspect ratio trapping (ART) Idea: Based on ELO concept but no merging High aspect ratio windows (trenches) to catch all defects Progress lead by IMEC, Sematech Completely compatible with Si CMOS fin processes (replacement fin) IMEC VLSI 2016 Mattias Borg / More than Moore Future of Electronics 26

28 Defect trapping in ART Defects (dislocation threading, twins, stacking faults) occur on (111) planes Defects across the trenches terminate on oxide Defects along the trench may not be trapped IMEC etches v-groove + nucleation layer at low T creates dense twin network at heterojunction Julian et al JCG 2014 Orzali et al. JAP 2015 Waldron et al. SSE 2016 (IMEC) Mattias Borg / More than Moore Future of Electronics 27

29 Strategies - Nanowire epitaxy Created by highly anisotropic growth rate High in one direction, low in all others Usually growth in [111]B direction (vertical) Seed particles (Au, Ag, Al, Sn,...) Self-assisted (Ga GaAs, In InAs) Selective area nanoepitaxy Tomioka et al. Nature 2012 Limits defect generation by small footprint Plissard et al. Nanotechn Mattias Borg / More than Moore Future of Electronics 28

30 Strategies - Template-assisted selective epitaxy (TASE) A combination of ELO, ART, and nanowire growth Key concepts: 1. Limit epitaxy to start from a single nucleation point 2. Assist the crystal growth to desired shape by confining epitaxy within an oxide template. In practice Vertical process Horizontal process On bulk Si Co-planar with Si Borg et al. Nano Letters 2014 Schmid et al. APL 2015 Mattias Borg / More than Moore Future of Electronics 29

31 High material quality Defects contained at heterojunction Crystal twin defects often present High carrier mobility 23 nm InAs: µ n = 5400 cm 2 /Vs 20 nm GaSb: µ p = 760 cm 2 /Vs Ballistic transport < 50K [110] InAs Si TiN InAs Mattias Borg / More than Moore Future of Electronics 30

32 Flexible horizontal geometries ~23 nm Si InAs Flexible geometries: Fins, sheets, crosses Branched structures 1D networks? 200 nm Dense packing density, compatible with < 10N Mattias Borg / More than Moore Future of Electronics 31

33 Cointegration of multiple materials Sequential repetition of TASE allows for multiple channel materials densely spaced. III-V CMOS Communication Photonic devices Quantum transport = All on one chip Cutaia et al. VLSI 2016 Schmid et al. IEDM 2016 Mattias Borg / More than Moore Future of Electronics 32

34 Integrated III-V devices Nanowires ART TASE InAs fin I on = 140 μa/μm (V DS =0.5V) g m = 1.6 ms/μm (V DS =0.5V) µ FE ~ 1200 cm 2 /Vs SS = 90 mv/dec f t = 25 GHz f max = 48 GHz I on = 200 μa/μm (V DS =0.5V) g m = 1.3 ms/μm (V DS =0.5V) µ FE ~ 1200 cm 2 /Vs SS = 82 mv/dec 23x25 nm I on = 480 μa/μm (V DS =0.5V) g m = 0.9 ms/μm (V DS =0.5V) µ FE ~ 500 cm 2 /Vs SS = 250 mv/dec Berg et al. EDL 2016 IMEC VLSI 2016 Schmid et al. APL 2015 Mattias Borg / More than Moore Future of Electronics 33

35 Summary Heterogeneous systems can add functionality, better performance and efficiency to circuits 3D Integration Monolithic (III-V) integration Chips/wafers are stacked and connected Adding functionality without area cost High cost, high yield Very flexible Devices are formed coplanar with Si or in a plane above Epitaxial methods dominate Low cost, High density Not as flexible Mattias Borg / More than Moore Future of Electronics 34