Chip-to-Wafer Technologies for High Density 3D Integration

Transcription

1 Chip-to-Wafer Technologies for High Density 3D Integration CEA Leti Minatec Campus, STMicroelectronics, SET, CNRS Cemes, Air Liquide Electonics Systems May 11, 2011

2 A collaborative work CEA Leti Minatec Campus: T. Signamarcheix, L. Bally, L. Sanchez, M. Francou, S. Verrun, E. Augendre, L. Di Cioccio, V. Carron, C. Deguet and N. Sillon STMicroelectronics: R. Taibi, A. Delolme, A. Farcy and B. Descouts SET: G. Lecarpentier CNRS Cemes: M. Legros and M. Martinez Air Liquide Electronics Systems: V. Lelievre 2

3 Chip-to-Wafer Technologies for High Density 3D Integration Introduction Direct Cu bonding gprocess SET FC300 with special design Alignment performance Electrical validation Conclusions 3

4 3D assembly by chip or wafer stacking Multifunction devices (heterogeneous integration) Repartitioning reduces area of individual chips (Yield improvement). reduces number of mask levels per die (Cost improvement). results in shorter global interconnect lines (Energy saving / performance improvement). 4

5 Chip-to-Wafer stacking through direct bonding Flexibility In size In technology / supplier High yield Known good dies Good overlay Benefits of direct bonding Low pressure Low temperature No underfill even at high interconnect density 5

6 Die-to-Wafer alignment chip SiO Cu 2 wafer Damascene processing determines die and wafer surface topography. Cu surface is recessed (dishing). Both chip and wafer surfaces are activated prior to bonding. 6

7 Die-to-Wafer placement chip wafer SiO 2 Cu Die is placed. Die is secured by direct SiO 2 -SiO 2 bonding (low force, room temperature). 7

8 Die-to-Wafer interconnection chip wafer SiO 2 Cu Cu - Cu direct bonding: occurs during collective e annealing. is driven by Cu thermal expansion. depends on Cu thickness, dishing and temperature. 8

9 Grain boundaries evolve with annealing. Grain growth at triple points Here: 400ºC 9

10 FC300 special design against particulate contamination 10

11 Effective particulate contamination control with special design FC300 FC300 special design FC300 in class 1000 environment in class 10 environment SP P2 sum of defects (>90nm)

12 Alignment control Infrared reading Chip Δy Wafer Left Right Δx 12

13 Axial alignment is controlled 1 µm and could be improved by working on calibration. Δy (µm) Left alignment pattern Δx (µm) ) Δy (µm Right alignment pattern Δx (µm) 13

14 Angular misalignment < 10-2 degree Wafer θ(º) 1,0E-2 5,0E-3 0,0E+0 Chip -5,0E-3-1,0E columns lines 14

15 Sample preparation for electrical measurements chip wafer SiO 2 Cu Si coarse grinding Si etch (TMAH) SiO 2 etch 15

16 Cu resistivity is as expected on each level. L=640µm W=3µm T=0.5µm chip wafer ρ = 21.7 ±0.2 nω m ρ = 20.8 ± 0.2 nω m 16

17 Current flow from Chip to Wafer L=640µm W=3µm T=2x0.5µm chip wafer 17

18 Bonded interconnects show identical resistivity as for Wafer-to-Wafer bonding 0,5 Die 6 Voltage (V) 0,25 0-0,1-0,05 0 0,05 0,1-0, Die 8 Die 11 Die 15 Die 16 Die 17 Die 22-0,5 Current t(a) Die 23 ρ = 20.9 ±0.2 nω m ρ = 20.8 nω m on Cu-Cu bonded wafers: R. Taibi et al., "Full characterization of Cu/Cu direct bonding for 3D integration", Proceedings 60th ECTC, pp , June

19 Current flow through multiple bonding contacts There are bonding contacts (3x3 µm²) with 7 µm pitch. 19

20 The long daisy chain shows very tight resistance distribution. 1 Die 1 Die 3 0,5 Die 6 Voltage (V V) 0-1E-3-5E-4 0E+0 5E-4 1E-3-0,5 Die 8 Die 11 Die 15 Die 16 Die 17-1 Current (A) ρ = 24.3 ±0.2 nω m Die 22 Die 23 This resistivity value probably contains a contribution from the bonding interface. 20

21 Conclusions Chip-to-Wafer assembly has been demonstrated through Pick & Place and direct Cu-Cu bonding. The benefit of the approach is to allow low temperature and low pressure die positioning, and to work without underfill even at high interconnect densisties. FC300 special design effectively reduces particulate contamination. Misalignment is 1 µm and could be reduced by improving the calibration procedure. Chip-to-Wafer electrical continuity was verified for the first time and is showed to behave as in Wafer-to-Wafer configuration. Characterization is on going and further results will be submitted to IEDM 2011 (R. Taibi et al.). 21

22 Acknowledgments This work has been performed in the frame of the PROCEED project founded by the French authorities (at both regional and ministerial levels) and by European authorities (FEDER). 22