Semiconductor Manufacturing Technology. Semiconductor Manufacturing Technology

Transcription

1 Semiconductor Manufacturing Technology Michael Quirk & Julian Serda October 2001 by Prentice Hall Chapter 17 Doping Processes

2 Common Dopants Used in Semiconductor Manufacturing Acceptor Dopant Group IIIA (P-Type) Element Atomic Number Semiconductor Group IVA Element Atomic Number Donor Dopant Group VA (N-Type) Element Atomic Number Boron (B) 5 Carbon 6 Nitrogen 7 Aluminum 13 Silicon (Si) 14 Phosphorus (P) 15 Gallium 31 Germanium 32 Arsenic (As) 33 Indium 49 Tin 50 Antimony 51 Table 17.1

3 CMOS Structure with Doped Regions p-channel Transistor N M p n-channel Transistor O K L I J LI oxide n n p STI p p STI n n n n STI p n p n F p p n-well E p-well n B C p epitaxial layer D G H p A p silicon substrate Figure 17.1

4 Common Dopant Processes in CMOS Fabrication Process Step Dopant Method A. p Silicon Substrate B Diffusion B. p - Epitaxial Layer B Diffusion C. Retrograde n-well P Ion Implant D. Retrograde p-well B Ion Implant E. p-channel Punchthrough P Ion Implant F. p-channel Threshold Voltage (V T ) Adjust P Ion Implant G. p-channel Punchthrough B Ion Implant H. p-channel V T Adjust B Ion Implant I. n-channel Lightly Doped Drain (LDD) As Ion Implant J. n-channel Source/Drain (S/D) As Ion Implant K. p-channel LDD BF 2 Ion Implant L. p-channel S/D BF 2 Ion Implant M. Silicon Si Ion Implant N. Doped Polysilicon Por B Ion Implant or Diffusion O. Doped SiO 2 P or B Ion Implant or Diffusion Table 17.2

5 Ion Implant in Process Flow Wafer fabrication (front-end) Wafer start Thin Films Polish Unpatterned wafer Completed wafer Diffusion Photo Etch Photoresist mask Test/Sort Implant Anneal after implant Hard mask (oxide or nitride) Used with permission from Lance Kinney, AMD Figure 17.2

6 Doped Region in a Silicon Wafer Dopant gas Oxide Diffused region Oxide N p Silicon substrate Figure 17.3

7 Diffusion Diffusion Principles Three Steps Predeposition Drive-in Activation DopantMovement Solid Solubility Lateral Diffusion Diffusion Process Wafer Cleaning DopantSources

8 Dopant Diffusion in Silicon Si Si Si Si Si Si Dopant Si Si Si Si Si Vacancy Si Si Si Si Si Si a) Silicon lattice structure b) Substitutional diffusion Si Si Si Si Si Si Si Si Si Displaced silicon atom in interstitial site Si Si Si Si Si Si Si Si Si Dopantin interstitial site c) Mechanical interstitial displacement d) Interstitial diffusion Figure 17.4

9 Solid Solubility Limits in Silicon at 1100 C Dopant Solubility Limit (atoms/cm 3 ) Arsenic (As) 1.7 x Phosphorus (P) 1.1 x Boron (B) 2.2 x Antimony (Sb) 5.0 x Aluminum (Al) 1.8 x Table 17.3

10 Diffusion Process Eight Steps for Successful Diffusion: 1. Run qualification test to ensure the tool meets production quality criteria. 2. Verify wafer properties with a lot control system. 3. Download the process recipe with the desired diffusion parameters. 4. Set up the furnace, including a temperature profile. 5. Clean the wafers and dip in HF to remove native oxide. 6. Perform predeposition: load wafers into the deposition furnace and diffuse thedopant. 7. Perform drive-in: increase furnace temperature to drive-in and activate thedopant bonds, then unload the wafers. 8. Measure, evaluate and record junction depth and sheet resistivity.

11 Typical Dopant Sources for Diffusion Dopant Formula of Source Chemical Name Arsenic (As) AsH 3 Arsine (gas) Phosphorus (P) PH 3 Phosphine (gas) Phosphorus (P) POCl 3 Phosphorus oxychloride (liquid) Boron (B) B 2 H 6 Diborane (gas) Boron (B) BF 3 Boron tri-fluoride (gas) Boron (B) BBr 3 Boron tri-bromide (liquid) Antimony (Sb) SbCl 5 Antimony pentachloride (solid) SEMATECH Diffusion Processes, Furnace Processes and Related Topics, (Austin, TX: SEMATECH, 1994), P. 7. Table 17.4

12 Ion Implantation Overview Controlling DopantConcentration Advantages of Ion Implant Disadvantages of Ion Implant Ion Implant Parameters Dose Range

13 Controlling Dopant Concentration and Depth Ion implanter Low energy Low dose Fast scan speed Ion implanter High energy High dose Slow scan speed Dopantions Beam scan Beam scan Mask x j Mask Mask Mask x j Silicon substrate Silicon substrate a) Lowdopantconcentration (n, p ) and shallow junction (x j ) b) High dopantconcentration (n, p ) and deep junction (x j ) Figure 17.5

14 General Schematic of an Ion Implanter Ion source Plasma Extraction assembly Analyzing magnet Ion beam Acceleration column Process chamber Scanning disk Figure 17.6

15 Advantages of Ion Implantation (from Table 17.5) 1. Precise Control ofdopantconcentration 2. GoodDopant Uniformity 3. Good Control ofdopant Penetration Depth 4. Produces a Pure Beam of Ions 5. Low Temperature Processing 6. Ability to Implant Dopants Through Films 7. No Solid Solubility Limit Table 17.5

16 Classes of Implanters Class of Implanter System Medium Current High Current High Energy Description and Applications Highly pure beam currents <10 ma. Beam energy is usually < 180 kev. Most often the ion beam is stationary and the wafer is scanned. Specialized applications of punchthrough stops. Generate beam currents > 10 ma and up to 25 ma for high dose implants. Beam energy is usually <120 kev. Most often the wafer is stationary and the ion beam does the scanning. Ultralow-energy beams (<4keV down to 200 ev) for implanting ultrashallow source/drain junctions. Beam energy exceeds 200 kev up to several MeV. Place dopants beneath a trench or thick oxide layer. Able to form retrograde wells and buried layers. Oxygen Ion Implanters Class of high current systems used to implant oxygen in siliconon-insulator (SOI) applications. Table 17.6

17 Range and Projected Range of Dopant Ion Incident ion beam Silicon substrate Stopping point for a single ion R p R p dopant distribution Figure 17.7

18 Projected Range Chart 1.0 Implanting into Silicon Projected Range, R p (µm) 0.1 B P As Sb ,000 Implantation Energy (kev) Redrawn from B.El-Kareh, Fundamentals of Semiconductor Processing Technologies, (Boston: Kluwer, 1995), p. 388 Figure 17.8

19 Energy Loss of an Implanted Dopant Atom Electronic collision Energetic dopantion Silicon crystal lattice Si Si Si Si Si Si X-rays Si Si Si Si Si Si Atomic collision Si Si Si Si Si Displaced Si atom Si Si Si Si Si Si Si Figure 17.9

20 Crystal Damage Due to Light and Heavy Ions Light ion impact Heavy ion impact Figure 17.10

21 Ion Implanters Ion Source Extraction and Ion Analyzer Acceleration Column Scanning System Process Chamber Annealing Channeling Particles

22 Schematic of Ion Source Chamber Ion beam Extraction assembly Extraction electrode Arc chamber Source chamber Extraction assembly Turbo pump Ion source insulator Bernas ion source assembly Used with permission from Applied Materials Technology, Precision Implanter 9500 Figure 17.11

23 Schematic of Bernas Ion Source Arc chamber Front Plate Vapor nozzle Oven Anode 100 V Arc Chamber Aperture Electron repeller Gas feed tube 5 V Gas inlets Filament Electron reflector DI cooling water inlet Dopantgas inlet Used with permission from Applied Materials Technology, Precision Implanter 9500 Figure 17.12

24 Interaction of ion Source and Extraction Assemblies Ion Source Extraction Assembly Source magnet supply N S Grounded electrode Suppression electrode Arc chamber Ion beam To PA N S 2.5 kv Suppression 5V Filament 120 V Arc 60 kv Extraction Terminal reference (PA voltage) Used with permission from Applied Materials Technology, Precision Implanter 9500 Figure 17.13

25 Analyzing Magnet Ion source Extraction assembly Analyzing magnet Ion beam Lighter ions Neutrals Heavy ions Graphite Figure 17.14

26 Dose Versus Energy Map Dose (atoms/cm 2 ) Present applications Evolving applications Source/drain Channel and drain engineering V t adjust Poly doping Damage engineering Buried layers Retrograde wells Triple wells Proximity gettering ,000 Energy (kev) Used with permission from Varian Semiconductor Equipment Figure 17.16

27 Linear Accelerator for High-Energy Implanters Atomic mass analysis magnet Linear accelerator Final energy analysis magnet Source Scan disk Wafer Figure 17.17

28 Space Charge Neutralization Cross section of beam with space charge neutralization Cross section of beam blow-up Dopantion Secondary electron Figure 17.18

29 Neutral Beam Trap Analyzing Magnet Focussing anode Neutral beam trap Neutral beam path Grounded collector plate Source Accelerator Ion beam Y-axis deflection X-axis deflection Wafer Used with permission from Varian Semiconductor Equipment Figure 17.19

30 Electrostatic Ion Beam Scanning of Wafer Low frequency Y-axis deflection High frequency X-axis deflection Ion beam Y-axis deflection Wafer X-axis deflection Twist Tilt Figure 17.20

31 Implant Shadowing Ion beam Ion beam Resist Resist a) Mechanical scanning with no tilt b) Electrostatic scanning with normal tilt Figure 17.21

32 Electron Shower for Wafer Charging Control Secondary electron target -Biased aperture Secondary electrons Wafer Ion beam Electron gun Ion - electron recombination Adapted from Eaton NV10 ion implanter, circa 1983 Figure 17.23

33 Plasma Flood to Control Wafer Charging Neutralized atoms Ion beam Chamber wall Electron emission Wafer scan direction -Biased aperture Plasma electron flood chamber N S Ar Ar Ar N S Current (dose) monitor Argon gas inlet Figure 17.24

34 Faraday Cup Beam Current Measurement Scanning disk with wafers Sampling slit in disk Suppressor aperture Faraday cup Ion beam Current integrator Scanning direction Redraawn from S. Ghandhi, VLSI Fabricaton Principles: Silicon and Gallium Arsenide, 2d ed., (New York: Wiley, 1994), p. 417 Figure 17.26

35 Annealing of Silicon Crystal Ion Beam Repaired Si lattice structure and activated dopant-silicon bonds a) Damaged Si lattice during implant b) Si lattice after annealing Figure 17.27

36 Silicon Lattice Viewed Along <110> Axis Used with permission from Edgard Torres Designs Figure 17.28

37 Ion Entrance Angle and Channeling <100> <110> <111> Used with permission from Edgard Torres Designs Figure 17.29

38 Implantation Damage from Particulate Contamination Ion implanter Beam scan Mask Mask Particle creates a void in implanted area Silicon Substrate Figure 17.30

39 Ion Implant Trends in Process Integration Examples of Different Implant Processes Deep buried layers Retrograde wells Punchthrough stoppers Threshold voltage adjustment Lightly doped drain (LDD) Source/drain implants Polysilicongate Trench capacitor Ultra-shallow junctions Silicon on Insulator (SOI)

40 Buried Implanted Layer Retrograde wells n-well p-well p Epilayer p Buried layer p Silicon substrate Figure 17.31

41 Retrograde Well n-typedopant p-typedopant n-well p-well n p p Buried layer p Silicon substrate Figure 17.32

42 Punchthrough Stop n-typedopant p-typedopant n-well n n p-well p p p Buried layer p Silicon substrate Figure 17.33

43 Implant for Threshold Voltage Adjustment n-typedopant n-well n n n p-typedopant p-well p p p p Buried layer p Silicon substrate Figure 17.34

44 Source-Drain Formations p-channel transistor p LDD implant Poly gate n-channel transistor n LDD implant p S/D implant Spacer oxide n S/D implant Source n-well Drain p Buried layer Source p Silicon substrate p-well Drain a) p andn lightly-doped drain implants (performed in two separate operations) Source Drain n-well p Buried layer p Silicon substrate Source Drain p-well b) p and n Source/drain implants (performed in two separate operations) Figure 17.35

45 Dopant Implant on Vertical Sidewalls of Trench Capacitor Trench for forming capacitor n dopant Tilted implant n p Figure 17.36

46 Ultra-Shallow Junctions Poly gate 180 nm 54 nm arsenic implanted layer 20 Å gate oxide Figure 17.37

47 CMOS Transistors with and without SIMOX Buried Oxide Layer n-well p-well n-well p-well Epi layer Silicon substrate Implanted silicon dioxide Silicon substrate Silicon substrate a) Common CMOS wafer construction b) CMOS wafer with SIMOX buried layer Figure 17.38