Integration/Reliability Issues for Cu/low-k BEOL Interconnects

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IEEE Workshop on Microelectronics and Electron Devices, April 3, 2009, Boise Integration/Reliability Issues for Cu/low-k BEOL Interconnects Daniel C.

1 IEEE Workshop on Microelectronics and Electron Devices, April 3, 2009, Boise Integration/Reliability Issues for Cu/low-k BEOL Interconnects Daniel C. Edelstein IBM Fellow and Manager, BEOL Technology Strategy IBM T. J. Watson Research Center, Yorktown Hts., New York 2007 IBM Corporation

2 Outline From an integration perspective, discuss scaling impacts on reliability of: Metals Insulators Chip-Package Interaction (CPI) Summarize for each key issues, proposed solutions, key metrics, analytical techniques 2 D. Edelstein, April 3, IBM Corporation

Dielectric reliability Via/line interface Liner-seed and Cu fill

3 Outline Technology Map Underfill Crackstop Chip-Package 45 nm 90 nm Vacuum ( Air- ) Gaps Cap reliability Dielectric-Cap adhesion Dielectric reliability Via/line interface Liner-seed and Cu fill Cu electromigration 3 D. Edelstein, April 3, IBM Corporation

4 Summary Metals Issues: Cu gapfill, Cu grain growth, electromigration scaling, new materials in liner/seed Proposed solutions: Noble-like metal in liner, selective metal cap, Cu-alloy seed Critical Metrics: Via yields, Cu resistivity, defectivity, electromigration, stressmigration Analytical: Cu/barrier interfacial diffusivity and E a, Cu grainsize, metal interdiffusions, galvanic potentials, TEM/EELS, tomography, other microprobes Insulators Issues: Low-k mechanical and dielectric strengths, process damage, damascene pattern integrity Proposed solutions: Incremental k reduction, re-optimization of film properties, modify skeleton Critical metrics: Patterning, wire C, I-V, Vbr, TDDB, tensile stress, modulus, chip-package reliability Analytical: Electrical, mech. modeling, modulus/hardness, adhesion, fracture toughness, pore size, porosity, plasma-induced damage Chip-Package Issues: TCE mismatches, tensile low-k, weak low-k and pkg. polymers, larger chips, Pb-free C4 s Proposed solutions: Tough crackstop, maximized low-k strength and adhesion, ideal underfills, chip-join thermal budgets, reduced-tce laminates (cores), compliant leads, Si Carrier Critical metrics: Deep thermal cycle reliability, T/H/B, etc., underfill toughness and fatigue Analytical: Sonoscan, failure analyses techniques, polymer Kc and fatigue 4 D. Edelstein, April 3, IBM Corporation

5 Acknowledgements This work was done by countless colleagues from IBM and our R&D Alliance partners, at: T. J. Watson Research Center, Yorktown Hts., NY Nanotechnology Center, Albany, NY Semiconductor and Packaging R&D Centers, E. Fishkill, NY 5 D. Edelstein, April 3, IBM Corporation

6 Data Section IEEE WMED 6 D. Edelstein, April 3, IBM Corporation

Impact of Electron Scattering in Nanoscale Cu Wires Extracted Cu Resistivity vs. Wire Cross-Sectional Area 3.6x10-6 3.4x10-6 3.

7 Impact of Electron Scattering in Nanoscale Cu Wires Extracted Cu Resistivity vs. Wire Cross-Sectional Area 3.6x x x10-6 ρ = RA Cu L 3-4 TEMs per datapoint Data fit to: ρ = ρ o (1+Cλ/A) a) b) M1 Cu ρ ( Ω -cm ) 3.0x x x x10-6 ITRS 32 nm node ρ~3.9 µωcm ITRS 45 nm node ρ~3.0 µωcm ρ o = 2.01 ± 0.02 E-6 Ω-cm C = 580 ± 45 Ωcm. nm λ = 3 nm Able to predict ρ for future technology nodes c) 2.2x x10-6 ITRS 65 nm node ρ~2.5 µωcm 1.5x Line Area (nm 2 ) L. Gignac, AMC 2007 Cu resistivity increases as Cu wire area decreases. Cu grain size does not influence ρ greatly when grain size > electron mean free path. In the above case, surface scattering is the major factor. TCR method in literature overestimates ρ. 7 D. Edelstein, April 3, IBM Corporation

8 Extendibility Problem: Electromigration Lifetime Reduction Scaling in Cu Damascene Lines Interfacial diffusion SiCNH Void surface gb diffusion Marker Velocity Interfacial diffusion Ta 1 Grain-boundary diffusion degrades Cu electromigration reliability in nanowires t 50 /t 50 (1.3x0.9) 0.1 Theory liner Void h Cu e t 50 (h) 10 3 Wf B w(µm) Q EM (ev) Cu linewidth, grain size Blocking material L cr xh (µm 2 ) C-K. Hu, IRPS 2004 and IITC Top Cu/cap interface dominates E-M diffusion for bamboo lines Scaling trend is predictable by geometry, with no adjustable parameters Lifetime drops as dimension shrinks now dropping at 50%/generation At the same time, chip current density requirements scale up Cu lines at 45 nm node and beyond have reduced bamboo grains further impact 8 D. Edelstein, April 3, IBM Corporation /T (10-4 K -1 )

9 Approaches to Recover Cu Electromigration Reliability vs. Scaling Bamboo (Cu grainsize solved) Non-Bamboo (Cu grains not solved) Selective Metal Cap (Shut down top-surface Cu diffusivity) e.g. electroless CoWP impacts: leakage, TDDB, manufacturability Flash noble liner layer on TaN/Ta (Increase Cu grain growth?) e.g. PVD (Ta)Ru, CVD-Ru or Co impacts: reduced Cu volume %, galvanic corrosion potential, CMP difficulties Doped Cu seed (Stuff small Cu grain boundaries) e.g. Cu(Al) impacts: Cu resistivity, linewidth-dependence, dilute alloy control in mfg. 9 D. Edelstein, April 3, IBM Corporation

One Solution to Cu Electromigration Scaling Problem: Selective Metal Caps example: electroless CoWP For bamboo lines: Selective top metal cap can eliminate EM issue completely Activation energy can

10 One Solution to Cu Electromigration Scaling Problem: Selective Metal Caps example: electroless CoWP For bamboo lines: Selective top metal cap can eliminate EM issue completely Activation energy can reach to bulk Cu values Current densities are then limited to much higher values by rms joule heating For small-grained lines: Grain boundary diffusion may still dominate electromigration lifetimes C-K. Hu, IRPS 2004 Challenges: Remedy insufficient Cu recrystallization or Cu grain boundary diffusion (e.g. by alloy) Achieve manufacturable selective metal capping process with a uniform ~few nm cap, and no impact to shorts yield, line-line leakage, or dielectric breakdown reliability 10 D. Edelstein, April 3, IBM Corporation

Selective CVD-Ru Metal Cap Opens and Shorts

11 Selective CVD-Ru Metal Cap Opens and Shorts Yields Blanket Deposition Rates TDDB Reliability Microanalysis Selectivity Performance Electromigration Reliability Test Chips C-C. Yang, et al. submitted to IITC D. Edelstein, April 3, IBM Corporation

Another Approach - Cu-Alloy Seedlayer for E-M Enhancement Electromigration Cu Resistivity Pileup of Al dopant at Cu/cap interface reduces fast-path Cu E-M Adding certain dopants to the Cu seedlayer

12 Another Approach - Cu-Alloy Seedlayer for E-M Enhancement Electromigration Cu Resistivity Pileup of Al dopant at Cu/cap interface reduces fast-path Cu E-M Adding certain dopants to the Cu seedlayer can enhance E-M reliability but at the expense of Cu resistivity and linewidth-dependence and other potential mfg. control issues Need to determine best dopant and its % in Cu for optimal R vs. E-M. Numerous candidates studied over the years, most rejected Aluminum has emerged as a good candidate Several companies have adopted Cu( 1 at.% Al) in production since 65/45 nm S. Yokogawa, et al., IEEE IRPS D. Edelstein, April 3, IBM Corporation

13 Cu Metallization Gapfill Extendibility Problem Via yield and reliability are based on liner/seed/plating process window that is determined by Cu seed process window, comprised of: Reactive Ion Etch (RIE) patterning Liner pinch-off above, and continuity below Seed pinch-off above, and continuity below Plating (seed etching and superfill rates) 13 D. Edelstein, April 3, IBM Corporation

Extendibility of Cu Damascene Metallization: Add Noble Metal to Ta-Based Barrier ECD-Cu PVD-Cu PVD Ta(Ru) or

9 PVD PVD PVD/CVD BEOL: Yang et al., IITC 2006 Cu contacts: Seo et al., AMC 2008 TaN/Ta TaN/Ta 0.1 Ru 0.

Retain high-integrity PVD-Cu/barrier interface for electromigration (e.g. Ta/Cu, not Ta 2 O 5 /Cu) Increase thin Cu seed wettability and continuity in small, high a.

(terminal effect), CMP, Cu fill volume (Cu line resistance) New concerns for galvanic corrosion, Cu/barrier

14 Extendibility of Cu Damascene Metallization: Add Noble Metal to Ta-Based Barrier ECD-Cu PVD-Cu PVD Ta(Ru) or CVD-Ru PVD-Ta PVD-TaN PVD PVD PVD BEOL: Nogami et al., AMC 2008 TaN/Ta TaN/Ta 0.3 Ru 0.7 TaN/Ta 0.1 Ru 0.9 PVD PVD PVD/CVD BEOL: Yang et al., IITC 2006 Cu contacts: Seo et al., AMC 2008 TaN/Ta TaN/Ta 0.1 Ru 0.9 TaN/Ta/Ru Retain ECD-Cu gapfill process window and Cu reliability with minimal integration disruption Retain high-integrity PVD-Cu/barrier interface for electromigration (e.g. Ta/Cu, not Ta 2 O 5 /Cu) Increase thin Cu seed wettability and continuity in small, high a.r. features Provide good plating nucleation inside Cu-seed discontinuities Minimal impacts to plating (terminal effect), CMP, Cu fill volume (Cu line resistance) New concerns for galvanic corrosion, Cu/barrier adhesion and electromigration 14 D. Edelstein, April 3, IBM Corporation

10 ma V1 to M2 TaN/Ta TaN/TaRu90% TaN/Ta Lifetime (au) TaN/TaRu90% More than 3X longer

15 Cu Electromigration Performance with TaN/TaRu Barrier Cumulative Failure Probability(%) T = 300 o C, I = 0.10 ma V1 to M2 TaN/Ta TaN/TaRu90% TaN/Ta Lifetime (au) TaN/TaRu90% More than 3X longer lifetimes Recovered normal reliability by fixing defective Cu gapfill 15 D. Edelstein, April 3, IBM Corporation

Testing New Barrier Properties Oxidation Barrier Test (310C/8 days

(Triangular Voltage Sweep, 300C, 1 MV/cm TaRuN90% TaRuN70% TaRu90%

Ta, TaN >> TaRu70% > TaRuN70% > TaRu90% > TaRuN90% No Cu oxidation

films do not fully block Cu + or O 2 diffusion.

16 Testing New Barrier Properties Oxidation Barrier Test (310C/8 days in air) TaRuN90%/TaRu90% TaRuN70%/TaRu70% Cu+ Barrier Test (Triangular Voltage Sweep, 300C, 1 MV/cm TaRuN90% TaRuN70% TaRu90% Cu is oxidized TaN/TaRu90% Cu is oxidized TaN/Ta TaRu70% Ta TaN Ta, TaN >> TaRu70% > TaRuN70% > TaRu90% > TaRuN90% No Cu oxidation No Cu oxidation TaN/Ta = TaN/TaRu90% >> TaRuN/TaRu PVD TaRu(N) films do not fully block Cu + or O 2 diffusion. PVD TaN and/or Ta is required underneath TaRu. 16 D. Edelstein, April 3, IBM Corporation

Extendibility of the Most Reliable Via/Line

ULK with new process ULK with old process 99.

1463 low stress low stress percentile 99 95

stress gradient max stress C-C. Yang, et al.

10 5 1 Cu is 500 X better than Al(Cu) at

011 10 100 1000 Stress Failure Time (hrs.) D.

17 Extendibility of the Most Reliable Via/Line Contacts 90 nm CMOS 65 nm CMOS 45 nm CMOS ULK with new process ULK with old process 99.9 V2 -> M2; T50 = hrs. σ = low stress low stress percentile stress gradient max stress stress gradient max stress C-C. Yang, et al., AMC (2008) Cu is 500 X better than Al(Cu) at 300C Stress Failure Time (hrs.) D. Edelstein, et al., IEEE IRPS (2004). A. Fischer, et al., IEEE IRPS (2007). 17 D. Edelstein, April 3, IBM Corporation

Advanced Dielectrics Roadmap: current IBM status 90nm Technology nodes 45nm 65nm 32nm 22nm 15nm SiCOH k=3.0 SiCOH k=2.7 PECVD Films psicoh k=2.4 psicoh k=2.2 psicoh k=2.

18 Advanced Dielectrics Roadmap: current IBM status 90nm Technology nodes 45nm 65nm 32nm 22nm 15nm SiCOH k=3.0 SiCOH k=2.7 PECVD Films psicoh k=2.4 psicoh k=2.2 psicoh k=2.0 Implementation Availability A. Grill, AMC 2007 and MRS 2009 Leading development and implementation of industry s most advanced low-k and ultralow-k PECVD dielectrics 18 D. Edelstein, April 3, IBM Corporation

19 Low-k and Ultralow-k Time-Dependent Dielectric Breakdown (TDDB) Low-k obeys root-e kinetics at least, and may be more robust Cu reduces lifetimes and plays an important role Moisture is bad Line-edge roughness affects lifetimes J. Lloyd, AMC D. Edelstein, April 3, IBM Corporation

20 Methodology of Fracture Mechanics excerpts from X-H. Liu, MRS 2009 invited talk G < Γ G: energy release rate G: fracture strength structure and geometry chemical bonding film stress interaction with environment thermal expansion and modulus channel cracking cohesive vs. adhesive failure delamination BEOL film fabrication chip packaging interaction Issue: Low-k C-doped SiOx glass films, the industry de facto standard, are unfortunately always tensile-stressed and have relatively low moduli and fracture toughnesses X.H. Liu et al, IITC (2004) AMC (2004) 20 D. Edelstein, April 3, IBM Corporation

21 Low-k Insulators Strengthening Low-k and Ultralow-k SiCOH Interfacial Region Historically, chronically low SiCOH adhesion results Typical pretreatments did not improve Discovered weak nucleation layer at interface Solution became clear graded nucleation Dramatic adhesion improvement, approaching ~bulk cohesive strength adhesion layer SiCHN Si Bulk SiCOH Extendible to ultralow-k porous SiCOH (not trivial) Identifiable by TOF-SIMS profiles of thin samples SiCOH Version G = 2.1 J/m 2 Control - no optimization Bulk-only SiCOH (J/m 2 ) Adhesion Strength Substrate Treatment (J/m 2 ) G = 5.0 J/m 2 With optimization Optimized Transition (J/m 2 ) Cohesive Strength (J/m 2 ) k= k=2.7 k= n/a A. Grill et al., MRS Spring D. Restaino et al., AMC S. Molis et al., SIMS Workshop D. Edelstein, April 3, IBM Corporation

22 Effect of Multilevel Metallization X-H. Liu, MRS 2009 invited talk fat wires thin wires substrate crack arrest on cap channel crack propagation Energy Release Rate Normalized Multiple metal levels Single metal level 0.0 Large enhancements in G possible with patterned metal under layers J.M. Ambrico, E.E. Jones, and M.R. Begley, (2002) Int. J. Solids and Struct, 39, pp Gap Width Normalized 22 D. Edelstein, April 3, IBM Corporation

23 Effects of Caps X-H. Liu, MRS 2009 invited talk Cap stiffness is important to prevent cracking. 50 varying modulus varying thickness 45 G max /G Cap layer acts like a spring holding the metal pads together. Strength of spring is proportional to the cap thickness X Cap Modulus Modulus x Thickness (knm) 23 D. Edelstein, April 3, IBM Corporation

Tunneling cracks may form in the SiCN cap

24 Spontaneous Cracking X-H. Liu, MRS 2009 invited talk 4 Levels in psicoh Spontaneous cracking observed in structures with a narrow gap. Tunneling cracks may form in the SiCN cap dielectric. Si SiO 2 4 levels in SiCOH 24 D. Edelstein, April 3, IBM Corporation

25 Finite Element Modeling of ULK Films in BEOL Structures To optimize ULK mechanical properties and wiring groundrule limits, and compute maximum strain energy release rate before channel cracking 4X EB 2X B2 M3 1X Film Stress Normalized Channel Cracking X.Liu et al., ASME 2006 Energy release rate (crack driving force) increases with # levels in stack Most sensitive to (tensile) stress, somewhat sensitive to modulus 1 Cohesive Strength Of Dielectric Safe Reduce ULK film stress and increase modulus to avoid cracking D. Edelstein, April 3, IBM Corporation 4 5 Modulus Normalized Energy Release Rate Normalized E σ = σ int + α T 1 υ G=A σ 2 h/e

26 Fundamental SiCOH Toughness Current (O)SG Universal Trend Universal curve determined by Si-O bond density 12.0 Cohesive Strength, Γ (J/m 2 ) Nominal Dielectric Constant, k Goal: Approach: Exceed universal curve for tougher PECVD ULK psicoh Reduce sensitivity to plasma-induced damage Improve molecular skeleton with Si-C-Si bonding but don t go too far! 26 D. Edelstein, April 3, IBM Corporation

27 DEMS BCHD IEEE WMED Ultralow-k Porous SiCOH Extendibility: Increase Cohesive Strength and Reduce Resistance to Plasma Damage Skeleton Precursor 2 PECVD 300 mm Production tool UV cure 300 mm Production tool Skeleton 1: DEMS (diethoxymethylsiloxane), strong Si-O x-linking, efficient porogen incorp. Porogen: BCHD (bicycloheptadiene) incorporates very efficiently, widely tunable k. Skeleton 2: (proprietary), adds Si-CH2-Si bonding for smaller pores, reduced plasma damage, increased toughness. k 2.4 pore size distributions from EP k 2.4 k 2.2 Property V1 V2 V1 V2 Modulus [Gpa] Stress [Mpa] Interface strength [J/m2] Porosity (%) dv/d(ln R) V1.0 Film Pore diameter (nm) 27 D. Edelstein, April 3, 2009 S. Gates, et al., AMC (2008) IBM Corporation

Advanced Porous SiCOH, K=2.2, at 32 nm Node 1x Dimensions K 2.2, V1 K 2.

damage Average line width reduced Trench bottoms improved Leakage

28 Advanced Porous SiCOH, K=2.2, at 32 nm Node 1x Dimensions K 2.2, V1 K 2.2, V2 K 2.2, V2 Effects of adding Si-C-Si bonding to Si-O-Si matrix Less pore connectivity, more Si-C bonds to break for damage less plasma-induced damage Average line width reduced Trench bottoms improved Leakage current reduced Net reduction in line capacitance for same k of film 28 D. Edelstein, April 3, 2009 S. Gates, et al., AMC (2008) IBM Corporation

Advanced Bilayer Low-k Cap Film SiCNx Low-k Adv barrier 98 350 o C 331 o C 302 o C 256 o C

SiCNy Cu Cumulative Failure Probability (%) 95 90 80 70 60 50 40 30 20 10 5 2 1 Passes E-M,

Barrier test Air barrier properties confirmed Si2.ls1 O1.ls1 C1.ls1 Cu1.

29 Advanced Bilayer Low-k Cap Film SiCNx Low-k Adv barrier o C 331 o C 302 o C 256 o C 218 o C SiCNx Adv. SiCNy Cu Cumulative Failure Probability (%) Passes E-M, S-M, and TDDB tests Relative Concentration (%) Passes O2 Barrier test Air barrier properties confirmed Si2.ls1 O1.ls1 C1.ls1 Cu1.ls1 τ (h) Achieves required keff reduction -5% N1.ls Sputter Time (min) 29 D. Edelstein, April 3, 2009 G. Bonilla, et al., AMC (2008) IBM Corporation

Airgap Technology Multilevel Airgap Wiring Demonstration on Advanced 65 nm

patterning for minimum (1x) levels No changes to standard Cu wiring process flow,

30 Airgap Technology Multilevel Airgap Wiring Demonstration on Advanced 65 nm Production Microprocessor 8x 8x 4x 2x 4x 2x 1x 1x Airgap process schemes applied to all Cu wiring levels above M1. Lithographic slots on larger (2x and above) levels Self-assembly sublithographic patterning for minimum (1x) levels No changes to standard Cu wiring process flow, fab tooling, or materials. Yield, performance, reliability, and modeling predictions demonstrated. 30 D. Edelstein, April 3, IBM Corporation

Comprehensive Airgap Performance/Reliability Assessment Capacitance modeling C reduction can be optimized to

cracking risk Thermal modeling sets current limits very small gap impact is calculated Electromigration good

stressing no issues in preliminary tests CDF (%) 99.00 90.00 50.00 10.00 5.00 1.00 Ungapped (Green) Gapped (Red) 1.

31 Comprehensive Airgap Performance/Reliability Assessment Capacitance modeling C reduction can be optimized to -40% CPU tuned performance estimates ~10% Fmax, ~15% active pwr Mechanical modeling Gap calculations find low cracking risk Thermal modeling sets current limits very small gap impact is calculated Electromigration good preliminary results Time-dependent dielectric breakdown good preliminary results Chip-package reliability stressing no issues in preliminary tests CDF (%) Ungapped (Green) Gapped (Red) 1.00E Time [hrs] Sonoscan after 1000 deep thermal cycles shows no fails We have seen some good preliminary indicators for manufacturability Need more extensive data, models, process windows for qualification 31 D. Edelstein, April 3, IBM Corporation

32 1. Corner Underfill Delam./Crack 2. C4/BEOL Delam. 3. BEOL Edge Delam. 4. Chip Fracture 32 D. Edelstein, April 3, IBM Corporation

33 1. Corner Underfill Delam/Crack 2. C4/BEOL Delam. Worst for ultra-large chips on organic laminates Increases with chip-size Cracks circumvent chip crackstop Fatal, independent of BEOL materials Limitations on available underfills, laminates Mitigation strategies required Flat vs. chip size above ~0.5 cm Worse for Pb-free C4 Can fail at weakest BEOL interface Mitigation strategies required 3. Edge BEOL Delamination Chip Fracture Chip-size, dicing, and BEOL low-k, ULK dependent Solved by tough crackstop and optimized dicing Crackstop toughness >> ULK, Si, SiO2, etc. Low-k and ULK optimized for adhesion/cohesion Primarily when chips are thinned Dicing and handling defects + stress Increases with chip size Fatal, independent of BEOL materials Mitigation strategies required 33 D. Edelstein, April 3, IBM Corporation

34 Crackstop Problem Overview(After Robert Cook 1994) X-H. Liu, MRS 2009 invited talk Si G, Γ Energy of dicing cracks during dicing process Maximum energy of delamination during DTC Si toughness Crackstop toughness position Interfacial adhesion (limited by ILD cohesive strength) 34 D. Edelstein, April 3, IBM Corporation

35 Method to Improve Crackstop Toughness X-H. Liu, MRS 2009 invited talk fibre toughening molding compound oxide ILD Silicon substrate 35 D. Edelstein, April 3, IBM Corporation

36 Measurement of Crackstop Effective Toughness Load Displacement for Multilevel ULK Build Isolated widths of crackstop structure 4-pt. bend load cell Crackstops Load (lbs) Delamination initiates Delamination pinned at loading points Delamination traveling In the unreinforced area 8-10 J/m2 4 J/m2 Delamination hits Crack stops Notch position Time (Secs) Produce chip with large areas of crackstop structure Mask designs includes multiple isolated crackstop designs 4 point bend test gives toughness of individual designs Load for failure of crack stop used to determine optimum design Fracture Energy Calculation: (1 ν ) Pc L G = Eb h T. Shaw et al., IITC D. Edelstein, April 3, IBM Corporation

Solving Cu/Low-k and Ultralow-k Chip-Package Interaction (CPI) Reliability example: 45 nm CMOS with low-k and ultralow-k wiring levels C4 BEOL Si Delaminations observed No Delaminations observed

after 1000 cycles of -55/+125C stress. 0 fails after 1800 cycles of -40/+125C stress. 0 CPI fails after 1000 cycles of -55/+125C Fundamental mechanical solutions enable ULK (k=2.

37 Solving Cu/Low-k and Ultralow-k Chip-Package Interaction (CPI) Reliability example: 45 nm CMOS with low-k and ultralow-k wiring levels C4 BEOL Si Delaminations observed No Delaminations observed after dicing optimization Relative Toughness Test chip Flip chip Wirebond Packaging MLC-LGA FCPBGA EPBGA Crackstop Toughness Interface CS1 CS2 Deep thermal cycle stress 0 fails after 1000 cycles of -55/+125C stress. 0 fails after 1800 cycles of -40/+125C stress. 0 CPI fails after 1000 cycles of -55/+125C Fundamental mechanical solutions enable ULK (k=2.4) to pass comprehensive CPI: Extensive finite-element modeling Optimized dicing Improved crackstop toughness Improved ULK adhesion S. Sankaran et.al., IEEE IEDM (2006). 37 D. Edelstein, April 3, IBM Corporation X25 Mold Si Mold Si Oxide SiCOH BPSG

38 Examples of Chip-Corner/Underfill Fail Mode Modeling is well understood for corner stresses, but not underfill fatigue Crack dives into BEOL structure damage found on multiple layers 38 D. Edelstein, April 3, IBM Corporation

Effect of impurity on Cu electromigration

Effect of impurity on Cu electromigration C.K. Hu, M. Angyal, B. Baker, G. Bonilla, C. Cabral, D. F. Canaperi, L. Clevenger, D. Edelstein, L. Gignac, E. Huang, J. Kelly, B. Y. Kim, V. Kyei- Fordjour, S.