TSV and Cu-Cu Direct Bond Wafer and Package-Level Reliability

Transcription

1 TSV and Cu-Cu Direct Bond Wafer and Package-Level Reliability K. Hummler 1, B. Sapp 1, J.R. Lloyd 2, S. Kruger 1, 2 S. Olson 1, 2, SB Park 3, B. Murray 3, D. Jung 3, S. Cain 3, A. Park 3, D. Ferrone 3, and I. Ali 1 1 SEMATECH, Albany, NY, USA; Klaus.Hummler@SEMATECH.org 2 College of Nanoscale Science and Engineering (CNSE), University at Albany, Albany, NY, USA 3 The State University of New York at Binghamton, Binghamton, NY, USA Abstract A comprehensive study of reliability failure modes in an advanced through-silicon via (TSV) mid process flow is presented in Part I of this paper. This is the first time unique TSV mid reliability failure modes at leading-edge TSV dimensions have been observed and reported. TSV Kelvin, comb and chain test structures with 10:1 aspect ratio and a TSV diameter of 5.5 µm are manufactured using a state-ofthe-art TSV process. Through standard BEOL reliability testing and physical failure analysis, we observe that the dielectric and barrier layers close to the bottom of the TSV and the TSV redistribution layer (RDL) interface emerge as the main sources of failures. Voltage ramp dielectric breakdown (VRDB) is compared with time-dependent dielectric breakdown (TDDB) measurements. It is found that VRDB correlates well with TDDB and can serve as a fast method for evaluating process changes or as an in-line process monitor. Copper-to-copper direct bonding (CuDB) is the leading candidate for ultra-high density chip-to-chip interconnects in 3D stacked ICs, because it has the potential to match leadingedge TSV pitches. It is important to consider the reliability aspects of the combined TSV and CuDB interconnect system in a package context. Part II of this paper reports on the design of a TSV and CuDB chip-package interaction test vehicle and first reliability results of the TSV / CuDB combined interconnect. Part I TSV Reliability Through-silicon vias (TSVs) are a key enabling technology for 3D and 2.5D (i.e., interposer-based) IC packaging. As such, the reliability of TSVs over the desired lifetime has to be demonstrated before TSV packaging-based products can go into high-volume manufacturing (HVM). Compared to conventional on-chip and package interconnect elements, TSVs are manufactured with significantly different structures and processes, which will likely result in new reliability failure modes. While there are several simulationbased studies of advanced TSVs, very few publications have reported actual reliability stress and characterization results [1, 2]. A recent paper by IBM [3] reports on TSV mid reliability for larger dimension TSVs, but does not provide any information on observed failure modes. The most recent papers [4,5,6,7,8,9,10,11] investigate TSVs with larger dimensions ( 10 µm) with one exception [5] which studied a 2 µm TSV last via. The majority of reliability tests are temperature cycling (TC) or electromigration (EM). Only one paper [10] focuses on the TSV dielectric breakdown and makes note that the Cu diffusion barrier coverage in the TSV is poor due to the scalloped sidewalls from the Bosch RIE process. Another reliability focus is on the adhesion and electromigration of solder joints between bonded chips and an interposer and chip. A recent review paper [12] summarizes the literature on solder-based bonding. In this study, we investigate the reliability failure modes of advanced geometry Cu-filled TSV mid structures under standard BEOL reliability stressing, including temperature cycling, electromigration and time-dependent dielectric breakdown. Stress and physical failure analysis (PFA) results are presented. In addition, voltage ramp dielectric breakdown is investigated as a potential method to evaluate TSV reliability. VRDB results are compared with traditional TDDB results to determine if any correlations can be made. If VRDB is able to predict TSV TDDB results with sufficient accuracy, it can be applied as a fast wafer-level process screening and monitoring method. Sample Fabrication Reliability samples are processed with the SEMATECH TSV mid flow. TSVs have an aspect ratio of ~10:1 with a diameter of 5.5 µm and a depth of 50 µm. They are lined with 0.3 µm of TEOS. PVD Ta/TaN provide a diffusion barrier, and CVD Ru precedes the PVD Cu seed deposition. The TSVs are filled void-free with a state-of-the-art bottom-up electroplating process and polished back to the MOL oxide. A single damascene Cu layer (M1) completes the front-side wafer processing. The wafers are then bonded to a full thickness silicon carrier wafer and thinned to approximately 58 µm. A wet etch is used to reveal the TSVs by ~2.5 µm above the surrounding silicon. TEOS is deposited over the TSV nails and polished back to reveal the Cu TSV fill. A onelayer Cu damascene RDL is formed on the back side for routing and contact to the test structures. For the first set of reliability results presented in the subsequent paragraphs, no passivation layers are present above front- or back-side metallization. The samples are diced without de-bonding from the carrier wafer. Reliability Results A. Temperature Cycling Temperature cycling between -55ºC and +155ºC with ramp rates of ±18ºC and dwell times of 5 minutes was performed in air. Sixteen samples each for single TSV Kelvin structures and 2960 TSV chain structures were stressed. The single via structures show no fails up to 500 cycles. About half of the TSV chains fail up to 255 cycles with a fairly wide 41

2 distribution in lifetimes, indicating a defect-driven mechanism. Some failures could not be confirmed in electrical failure analysis (EFA) and might be due to wire-bond issues caused by RDL corrosion. Figure 1 shows a failing TSV after mechanical cross-sectioning. The bottom of the TSV Cu fill is missing, most likely due to a process defect and delamination of the Cu fill (voiding or cracking). Figure 3. EM fail statistics (255ºC, 20 ma). Figure 1. TC fail after 250 cycles due to process defect during TSV Cu fill. B. Electromigration Figure 2 shows the test structure used for EM stressing. It consists of a 2 µm width RDL line connecting one upstream and one downstream TSV link. More than 10 samples each were stressed at 255ºC with an RDL current density of 2 MA/cm 2, 280ºC with 2 MA/cm 2, and 260ºC with 4 MA/cm 2. Lifetime distributions typical for Cu damascene metallization are observed in Figure 3, and PFA confirms that all failures occur in the RDL metallization rather than the TSVs. However, the quality of the TSV-RDL interface will influence the EM robustness. Figure 2 shows an example of an EM fail, which shows a reduced contact area between the upstream TSV and RDL, leading to current crowding and voiding in the RDL pad. Such a reduced contact area is typically caused by under-revealed TSVs [13]. Figure 2. EM fail (20 ma, 255ºC, 99 h). Left: RDL pad and line (TSV in pad center). Right: voiding in RDL line above upstream TSV. Reduced contact area (under-revealed TSV). C. Dielectric Breakdown TDDB stressing on this first set of investigations is performed comb-to-comb on a 3012 TSVs comb structure with minimum TSV spacing of 13 µm. At stress voltages above the threshold voltage (~5 V) of the MOS capacitor formed by the TSV, only half of the applied voltage drops over the TSV dielectric, because half of the TSVs will be in inversion and the other half in accumulation. Initial stressing at 100ºC and 20 V applied voltage did not result in any fails up to 555 h. Subsequently, the applied voltage was increased to 40 V, corresponding to a maximum field of ~1 MV/cm across the TEOS liner. The TSV dielectric experiences the maximum field close to the bottom sidewall of the TSV where the liner thins down to about 0.2 µm. Forty-eight samples were stressed at 40 V up to 655 h. The extrapolated time to 50% fails is reasonably high at 4,500 h. However, the slope is very shallow, again indicating defect-driven failure mechanisms (Figure 4). Since stressing is performed comb-tocomb, two dielectric failures are observed by photo emission microscopy (PEM) on all samples. For high confidence of defect localization, top-down as well as cross-sectional PEM is applied (Figure 5). Most samples analyzed with PFA show dielectric breakthrough toward the bottom of the TSV or at the substrate corner close to the TSV-RDL interface (Figure 6). Even though the dielectric and barrier layers are continuous (Figure 7), they are thinnest toward the bottom of the TSV, and electric fields are enhanced at the substrate corner. In addition, the back-side planarization process can cause damage to the TSV dielectric due to mechanical forces, especially in the case of over-revealed TSVs. Observations after partial CMP show that over-revealed TSVs are first bent over before being polished flat with respect to the surrounding TEOS [13]. Inspections have shown that damage to the RDL TEOS and the TSV dielectric liner can occur in this case (Figure 8). 42

3 Figure 7. Ta/TaN barrier coverage 25 µm down into the TSV (left) and close to the bottom of the TSV (right). Figure 4. TDDB failures vs. time (40 V, 100ºC). Figure 8. TSVs bent over after partial RDL dielectric CMP (strongly over-revealed TSVs). Figure 5. Top down (inset) and x-sectional PEM. Figure 6. TSV dielectric fail at RDL-side substrate corner. TDDB and VRDB Comparison In a second set of experiments, improvements to the test structure design and TSV processing are evaluated. VRDB and TDDB are used to assess these improvements, and to attempt establishing a correlation between TDDB and VRDB predictions. A. Test Structure Compared to the study above, the same comb test structures for TDDB and VRDB stressing were used. However, a substrate contact was added to avoid comb-tocomb stressing. Also, passivation layers were added above front- and back-side metallization to avoid issues with copper corrosion and moisture during stress. The comb structure has 3012 TSVs in the comb and 36 TSVs in each test pad. A substrate contact surrounds the comb structure forming a guard ring. A voltage sweep between the substrate contact and chuck shows that the substrate contact forms a Schottky diode (Figure 9), because no contact implant is performed. All TDDB and VRDB measurements were carried out with the 43

4 diode biased forward (high current). The voltage polarity for the forward-biased condition is present when the substrate contact is negative (ground) and the comb is positive. TDDB stressing was done by applying 40 V between the comb and substrate at 100 C in air. TDDB failure is defined as 100X or more increase from the initial leakage current. VRDB stress was done by increasing the voltage at a constant rate of 5.5 V/s between the comb and substrate from 0 V until failure. Measurements were done at 25 C and 100 C. VRDB failure is defined as an increase in leakage of at least 50% from the leakage at the previous voltage step and after a stable baseline leakage is established. Figure 9. I-V curve of the substrate contact shows a Schottky diode behavior. B. Sample Preparation Four M1 wafers were selected for TDDB and VRDB analysis. The wafers are from two different source lots (Lot 1 and Lot 2) and represent three unique process conditions. Table 1 provides a sample ID and the corresponding process details. The process variables explored were the post-tsv RIE clean, the TSV liner deposition method and the post-tsv plate anneal condition. There were two options for each of these variables. The TSV clean was either a 10 Å or 30 Å equivalent thermal oxide removal, the oxide liner was deposited by two different chemical vapor deposition recipes (liner A or liner B), and the post TSV plate anneal was 150 C/60 minutes or 350 C/30 minutes. coverage in the TSV compared to the 10 Å clean, because residual polymers after TSV RIE locally affect the dielectric liner deposition. C. Dielectric Breakdown Results Figure 10 shows a Weibull plot of TDDB result as a function of time. Based on the observation of very early fails and massive emission spots in PFA we conclude that split L2-10-A-150 is affected by an independent process issue and should not be considered in the analysis of the process splits. We still keep all data in the analysis to determine if a TDDB correlation to VRDB holds true for this process excursion. Comparison of the blue and red curves suggest that the longer clean and liner B give TSVs with better reliability performance than the shorter clean and liner A liner. VRDB was measured using portions from the same wafers as those used for TDDB. To illustrate a typical VRDB ramp, Figure 11 shows a representative VRDB I-V scan for each of the samples. Note that these individual curves don t represent the statistical distribution of all VRDB failures. Interestingly, both samples from Lot 1 have a quick ramp up to ~1 µa leakage current where it stabilizes until failure at V. L1-10-A-350 shows two different fails, the first is around 70 V and the second is at the same voltage as L1-30-B-350. This indicates that at least for the later fails, the two samples have a common failure mechanism and that a different failure mechanism is responsible for the early fails on L1-10-A-350, as observed by TDDB testing. Both samples from Lot 2 have much lower initial leakage currents than samples from Lot 1. However, L2-10-A-150 eventually ramps up to ~1 µa and has a short plateau before failing around 60 V. The most robust sample, L2-30-B-350 has an expected gradual increase in current as the voltage is ramped until a distinct failure around 160 V. Table 1. Process details of four front side completed sets of samples that were stressed under VRDB and TDDB. Figure 10. TDDB results showing the Weibull distribution as a function of time. We chose to monitor the electrical reliability as a function of these process changes, because TSV liner coverage was identified as a critical challenge for TSV scaling and TSV anneal condition were shown to effect Cu protrusions. We hypothesize that the 30 Å clean will improve the liner 44

5 Figure 11. Representative VRDB I-V scans. D. Failure Analysis for Front-side Completed TSVs Samples from Lots 1 and 2 were analyzed using photoemission microscopy. Both TDDB and VRDB samples stressed at 100ºC (except where noted) were analyzed to see if failure signatures differ between the two stressing methods. We chose samples from each process split and from similar failure percentiles. Samples from Lot 2 with a 10 Å clean and liner A have a unique emission signature compared to the other samples. The emission is massive and localized around the edge of the comb structures which suggests that the split L2-10-A-150 was affected by an independent processing issue. In general, the emission signatures are not a function of stressing method but rather fabrication process conditions. Initially, top-down depth analysis of four samples by attempting to bring the emission spot into best focus indicated that the failures are near the top of the TSV. However, x- sectional PEM analysis does not support this (Figure 12). An isolated emission spot from sample L2-30-B-350 reveals a failure located near the bottom of the TSV, in agreement with the preferred failure location observed in the TDDB work reported at the beginning of this report. Based on this finding, we don t recommend using the focus method to determine the depth of a failure. E. TDDB and VRDB Correlation Figure 13 shows the VRDB breakdown voltage plotted against the TDDB time to failure. The observation of TDDB time as an exponential function of observed VRDB breakdown voltage is in agreement with other studies reported in the literature [14]. Each color data set corresponds to a different wafer and the three points within each set correspond to the 20 th, 50 th, and 90 th percentile failures. This plot highlights the correlation between VRDB and TDDB. The data shows a good correlation of higher VRDB breakdown voltages with longer TDDB life times and vice versa. This plot also identifies two different correlation slopes, possibly related to different failure mechanisms. The relationship between VRDB and TDDB is shallow for samples with TDDB failure times below 100 minutes but steep for samples with TDDB failure times above 100 minutes. Photoemission failure analysis results also show some correlations with the two different sloped regions of this plot. Samples with TDDB failure times above 100 minutes (steep-sloped region) had <5 emission sites while samples with failure times on the shallower portion of this plot typically had > 15 emission sites and L2-10-A-150 had many failure sites. Based on the failure analysis, we hypothesize that the steep-sloped region correlates to TSV dielectric failures and the shallow sloped region correlates to a different failure mode. Cross sectional analysis of L2-30-B-350 (Figure 12) at TDDB failure time of 100 minutes showed that the failure mechanism is TSV dielectric-related. VRDB data was also generated at 25ºC, but the correlation to TDDB data is significantly worse. We conclude that VRDB should be performed at elevated temperatures for best prediction of TDDB data. With one additional mask, product TSVs can be wired together into capacitor arrays and tested immediately after TSV CMP and anneal, which results in very short wafer-level reliability feedback loops. Similar methods have been applied successfully in the past by wiring deep trench DRAM capacitors into large capacitor arrays directly after capacitor completion. Figure 12. Failure analysis images of sample L2-30-B-350. Left: top-down PEM image shows isolated emission spots; Right: x- section PEM shows the emission spot is located at the bottom of the TSV. Figure 13. VRDB breakdown voltage vs. TDDB time to failure of four different wafers. 45

6 Part II Reliability of Cu-Cu Direct Bond with TSVs Future 3D IC architectures, particularly for logic-on-logic or DRAM-on-logic stacking, will require a massive number of chip-to-chip interconnects (CCIs). Ideally, those interconnects should be on pitch with the TSVs providing the through substrate wiring. As TSV diameter and pitch scaling progresses, sub 10 µm pitches will be required for CCI. Solder-based CCI approaches suffer from inherent scaling limitations due the increased volume percentage of intermetallic compounds, which tends to limit interconnect reliability. Structurally, solder-based systems are limited by the extrusion of solder to the sides as well as interaction with underfill materials. Cu-Cu direct bonding (CuDB) doesn t exhibit many of these limitations and is considered the most promising candidate for scaling chip-to-chip interconnects to 10 µm pitch and below. In this paper we take first steps toward understanding CuDB reliability and chip-package interactions (CPI). Figure 14. CuDB interface with TSV. Figure 15. CuDB wafer stack process flow (top) and 3D package test vehicle schematic cross-section (bottom). Cu-Cu direct bond reliability Several papers have been published on CuDB processing but only a few papers focus on bond reliability [15,16,17,18]. These CuDB publications predominantly focus on EM and TC using simple BEOL cross bar structures and daisy chains. In contrast, this work shifts the focus to the combined system of TSVs and CuDB contact (Figure 14), which is most relevant for a 3D-stacked IC application. SEMATECH has developed CuDB technology in the context of a wafer-to-wafer bonding flow. The process flow and package construction are shown in Figure 15, and no carrier wafer is required. As we continue to push the CuDB process to lower temperatures, lower downforce, and shorter bonding times, we have assessed basic structural reliability aspects like bond strength and response to thermal cycling and thermal shock treatments. Robustness against thermal shock is not only relevant as a reliability criterion, but also as a prerequisite for successful post-cudb processing such as wafer back-side metallization and package assembly. Figure 16 shows that very high bond strengths were achieved at 195ºC and bond times as low as 2 minutes. The actual Cu-Cu bond strengths are even higher since the failures during 4-point bend testing occur at the Cu-SiO 2 interface and not at the Cu-Cu interface. Even when there is not much noticeable Cu grain growth across the initial bond interface (Figure 17), high bond strength and bulk Cu equivalent electrical conductivity can be achieved [19]. Figure point bend bond strength vs. bonding time for a 195ºC CuDB process. 46

7 Figure 17. TEM of 195ºC / 5 min CuDB interface. When considering the combined system of TSVs and CuDB interface, new phenomena emerge. Thermal shock treatments of a test vehicle with stacked TSV/CuDB structures at a 10 µm pitch were conducted by placing the stacked wafer onto an aluminum plate pre-heated to various peak temperatures. The face-to-face CuDB bonded wafer pair consists of a full thickness bottom wafer and a top TSV wafer thinned to 50 µm. Peak temperatures of 300ºC, 400ºC and 500ºC were investigated, and catastrophic failure is observed to varying degrees (Figure 18). Delamination occurs at the Cu- SiO 2 interface after just one cycle. The percentage of failing sites on the wafer is reduced as peak temperature is lowered, and slower thermal cycling to the same peak temperature does not result in the same failure. Simulations suggest that a combination of several factors contribute to this mechanism. When heat is applied to the surface of the die or wafer stack, the TSVs heat up faster than the surrounding silicon. This exacerbates the thermal expansion mismatch between the copper TSV and the silicon and leads to compressive stress in the CuDB interface and high tensile stress in the silicon. In case of high ramp rates and peak temperatures, this stress differential exceeds the adhesive strength of the Cu-SiO 2 interface. The failure only occurs when the TSV is directly bonded to another wafer via CuDB. The rigid CuDB interface prevents any stress relaxation by expansion or plastic deformation. We do not observe this failure mode when the TSV is temporarily bonded to a carrier wafer, most likely because the adhesive allows for some stress relaxation. This newly observed effect limits peak temperatures and ramp rates for processing of stacked TSV-CuDB structures which occurs after the joining of the CuDB interface. This includes not only wafer back-side processing but also assembly steps like die attach, solder reflow, etc. Similar to laminate package substrates, design rules may have to be devised which limit the number of TSVs and CuDB interfaces which can be stacked directly in the Z-direction before routing to the side to create stress relief. In this respect, we expect solder-based CCI stacked with TSVs to be more forgiving. Figure 18. Thermal shock treatment leads to delamination of CuDB-bonded top wafer in areas of dense TSV arrays. Cu-Cu direct bond and TSV chip-package interactions We have designed CuDB stacked test vehicle for the purpose of studying CPI of TSV and CuDB stacked structures. The test vehicle construction and processing is based on the flow described in Figure 15. The test vehicle contains many TSV and CuDB-related electrical and reliability test structures. At the time of print, hardware results were not available. A wealth of simulation data for this test vehicle has been generated in collaboration with Binghamton University and will be summarized in other papers [20]. Compared with a solder-based CCI we observe the following differences for a CuDB interface within a 3D IC package. Due to the small standoff and areal densities of up to 50% of copper in the CuDB interface, underfill is not required for thermal reasons. The thermal characteristics and bonding type (including unbonded interfaces with airgap) of the material surrounding the CuDB contact pads have a negligible effect on the thermal conductivity across the CuDB interface. A trade-off between stress levels in the CuDB interface and stress levels in the C4 interface with the package substrate is observed. CuDB technology at low stand-off tends to produce a much more rigid joining of stacked dies compared to solder-based methods with higher stand-off, which in turn results in higher stress levels for the C4 interface. Lowest C4 stress levels are observed when the material surrounding the CuDB contacts is not bonded and without CuDB underfill. Further studies by simulation and experiment are necessary to determine the sweet spot of this reliability trade-off. 47

8 Conclusions Unique failure modes for the TSV mid flow have been observed. Dielectric failures occur preferentially toward the bottom of the TSV. The TSV reveal and RDL processing steps are a source of defectivity for all performed reliability testing. VRDB is found to correlate very well with TDDB results, with the slope of the correlation indicating different failure mechanisms. VRDB on TSV short loop wafers is a powerful method for evaluating the effects of process changes on TSV dielectric reliability, and for wafer-level monitoring of TSV processing and reliability with very short feedback cycles. Although we recommend VRDB as an effective inline process monitor, it is not a replacement for TDDB because it does not give lifetime predictions. First studies for copper direct bond reliability and chippackage interactions have been conducted. A new failure mode during fast temperature cycling is observed for the combined system of TSVs and CuDB interface contacts. This failure mode is relevant for multi-stacked chips, and is not evident when TSVs or CuDB contacts are studied independently. Acknowledgments The authors thank the SEMATCH 3D Interconnect and CNSE Operations teams for wafer processing. We also thank Jay Gieseler for conducting the TSV TDDB and temperature cycling measurements. We thank Anil Kumar for design and layout work on the package interaction test vehicle. References 1. T. Frank et al., Reliability approach of high density Through Silicon Via (TSV), Electronics Packaging Technology Conference (EPTC), December, 2010, pp B. Majeed, D. Sabuncuoglu Tezcan, B. Vandevelde, F. Duval, P. Soussan, E. Beyne, Electrical characterization, modeling and reliability analysis of a via last TSV, Electronics Packaging Technology Conference (EPTC), December, 2010, pp M. Farooq et al., 3D copper TSV integration, testing and reliability, IEDM Conference, session 7.1, C. Y. Qianwen, C. Huang, Z. Tan, and Z. Wang, Reliability of through-silicon-vias (TSVs) with benzocyclobutene liners, Microelectronics Reliability, Ahead of Print T. Frank, S. Moreau, C Chappaz, P. Leduc, L. Arnaud, A. Thuaire, E. Chery, F. Lorut, L. Anghel, and G. Poupon, Reliability of TSV interconnects: Electromigration, thermal cycling, and impact on above metal level dielectric, Microelectronics Reliability, vol. 53, no. 1, pp , C. Cassidy, J. Kraft, S. Carniello, F. Roger, H. Ceric, A. P. Singulani, E. Langer, and F. Schrank, Through silicon via reliability, IEEE Transactions on Device and Materials Reliability, vol. 12, no. 2, pp , J. H. Lau, et. al., Feasibility study of a 3D IC integration system-in-packaging (SiP) from a 300 mm multi-project wafer (MPW), Journal of Microelectronics and Electronic Packaging, vol. 8, no. 4, pp , M. Bouchoucha, P. Chausse, S. Moreau, L-L. Chapelon, N. Sillon, and O. Thomas, Reliability study of 3D-WLP through silicon via with innovative polymer filling integration, IEEE Electronic Components and Technology Conference (ECTC), 61 st, 2011, pp S. W. Yoon, K. Ishibashi, S. Dzafir, M. Prashant, P. C. Marimuthu, and F. Carson, Development of super thin TSV PoP, IEEE Electronic Components and Technology Conference (ECTC), 61 st, 2011, pp K. Hideki, N. Maeda, K. Fujimoto, Y. Mizushima, Y. Nakata, T. Nakamura, and T. Ohba, Diffusion resistance of low temperature chemical vapor deposition dielectrics for multiple through silicon vias on bumpless wafer-on-wafer technology, Japanese Journal of Applied Physics, vol. 50, no. 5, Pt. 2, pp. 05ED02/1-05ED02/4, B. Bahareh, S. Ramalingam, K. Jagarajan, and R. Chaware, Advanced reliability study of TSV interposers and interconnects for the 28 nm technology FPGA, IEEE Electronic Components and Technology Conference (ECTC), 61st, 2011, pp C-T. Ko, and K-N. Chen, Reliability of key technologies in 3D integration, Microelectronics Reliability, vol. 53, no. 1, pp. 7-16, S. Olson, and K. Hummler, TSV Reveal Etch for 3D Integration, in Mitsumasa Koyanagi & Morihiro Kada, ed., '3DIC', IEEE, 2011, pp Y. Li, D. Velenis, T. Kauerauf, M. Stucchi, Y. Civale, A. Redolfi, and K. Croes, Electronic Components and Technology Conference (ECTC), 62 nd, IMEC, Leuven, Belgium May 29 - June , pp M. I. Riko, L. Peng, L. H. Yu, G. C. Lip, and T. C. Seng, Effect of direct current stressing to Cu-Cu bond interface imperfection for three dimensional integrated circuits, Microelectronic Engineering (Ahead of Print) L. Peng, L. Zhang, J. Fan, L. H. Yu, D. F. Lim, and T. C. Seng, Ultrafine pitch (6 μm) of recessed and bonded Cu-Cu interconnects by three-dimensional wafer stacking, IEEE Electron Device Letters, vol. 33, no. 12, pp , T. C. Seng, L. Peng, J. Fan, L. Hongyu, and G. Shan, Threedimensional wafer stacking using Cu-Cu bonding for simultaneous formation of electrical, mechanical, and hermetic bonds, IEEE Transactions on Device and Materials Reliability, vol. 12, no. 2, pp , L. Peng, H. Y. Li, D. F. Lim, S. Gao, and C. S. Tan, Thermal reliability of fine pitch Cu-Cu bonding with self assembled monolayer (SAM) passivation for wafer-on-wafer 3D-stacking, IEEE Electronic Components and Technology Conference, (ECTC) 61 st, 2011, pp J. Cho, S. Yu, M. P. C. Roma, S. Maganty, S. Park, E. Bersch, C. Kim, and B. Sapp, Mechanism of Low-Temperature Copper-to-Copper Direct Bonding for 3D TSV Package Interconnection, IEEE Electronic Components and Technology Conference (ECTC), 2013, in press. 20. A-Y. Park, D. Ferrone, S. Cain, D.Y. Jung, B. Murray, S. Park, and K. Hummler, Thermo-Mechanical Simulations of a Copper-to-Copper Direct Bonded 3D TSV Chip Package Interaction Test Vehicle, IEEE Electronic Components and Technology Conference (ECTC), 2013, in press. 48