Fabrication and Manufacturing (Basics) Batch processes
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1 Fbriction nd Mnufcturing (Bsics) Btch processes Fbriction time independent of design complexity Stndrd process Customiztion by msks Ech msk defines geometry on one lyer Lower-level msks define trnsistors Higher-level msks define wiring Silicon is net stuff Oxide protects things from impurities Cn be etched selectively on silicon or metl Cn be doped Add P or As impurities ECE 261 Krish Chkrbrty 1 Mking Chips Msks Chemicls Processing Processed wfer Chips Wfers ECE 261 Krish Chkrbrty 2 1
2 Fbriction Steps Fetures re ptterned on wfer by photolithogrphic process Photo-light lithogrphy, n. process of printing from plne surfce on which imge to be printed is ink-receptive nd the blnk re is ink-repellnt Cover the wfer with light-sensitive, orgnic mteril clled photoresist Expose to light with the proper pttern (msk) Ptterns left by photoresist cn be used to control where oxide is grown or mterils re plced on surfce of wfer ECE 261 Krish Chkrbrty 3 Bsic Processing Steps N-diffusion creted by doping regions of the substrte Poly nd metl re lid over the substrte, with oxide to insulte them from substrte nd ech other Wires re dded in lyers, lternting with oxide Vis re cut in the oxide ECE 261 Krish Chkrbrty 4 2
3 Bsic Fbriction Steps Lyout contins informtion on wht ptterns hve to mde on the wfer Msks re creted using the lyout informtion provided by the designer Procedure involves selective removl of the oxide Cot the oxide with photoresist, polymerized by UV light (pplied through msk) Polymerized photoresist dissolves in cid Photoresist itself is cid-resistnt ECE 261 Krish Chkrbrty 5 Bsic Processing Steps Strt with wfer t current step Add photoresist Pttern photoresist with msk Step-specific etch, implnt, etc. Wsh off resist ECE 261 Krish Chkrbrty 6 3
4 Design Rules Design rules govern the lyout of individul components: trnsistors, wires, contcts, vis How smll cn the gtes be, nd how smll cn the wires be mde? Conflicting Demnds: component pcking: more functionlity, higher speed Chip yield: smller sizes cn reduce yield (frction of good chips) Conservtive vs ggressive design rules ECE 261 Krish Chkrbrty 7 Foundry Interfce Lyout (msk set) Designer Foundry Design Rules Process Prmeters ECE 261 Krish Chkrbrty 8 4
5 Geometric Design Rules Resolution Width nd spcing of lines on one lyer Alignment mke sure intercting lyers overlp (or don t) Contct surround Poly overlp of diffusion Well surround of diffusion ECE 261 Krish Chkrbrty 9 SCMOS Design Rules Sclble CMOS design rules Feture size λ= hlf the drwn gte length (poly width) Mentor Grphics IC tool hs built-in design rule checker (DRC) Exmple design rules: Lyer Minimum Width Seprtion Metl 1 3 λ 3 λ Metl 2 3 λ 4 λ Poly 2 λ poly-poly: 2 λ poly-diff: 1 λ ECE 261 Krish Chkrbrty 10 5
6 Tub Ties nd Ltchup Substrte must be connected to power supply p-tub for nmos to V SS (Gnd) n-tub for pmos to Connections mde by specil vis clled tub ties Conservtive design rule: plce tub ties for every one or two trnsistors Why not plce one tie in ech tub tht hs 50 trnsistors? ECE 261 Krish Chkrbrty 11 Ltchup Too few ties: high resistnce between tub nd power supply, leds to prsitic bipolr trnsistors inhibiting norml chip opertion Prsitic silicon-controlled rectifier (SCR) When both bipolr trnsistors re off, SCR conducts no current SCR turns on: high current short-circuit between nd Gnd. p + n + n + p + p + n + n-well R nwell R nwell p-source R psubs p-substrte n-source R psubs () Origin of ltchup (b) Equivlent circuit ECE 261 Krish Chkrbrty 12 6
7 Stick Digrms Designing complete lyout in terms of rectngles cn be overwhelming Stick digrm: bstrction between trnsistor schemtic nd lyout Crtoon of chip lyout Replce rectngles by lines trnsistor (blue) p-type diffusion (yellow) Gnd Poly (red) n-type diffusion (green) Metl 1 (blue) V SS (Gnd) ECE 261 Krish Chkrbrty 13 Stick Digrm Metl 1 z b p-diffusion b b Gnd Poly n-diffusion Metl 1 Gnd ECE 261 Krish Chkrbrty 14 7
8 Some Lyout Hints Pln the globl structure ( big picture ), then design cells Floorpln Wiring strtegy Power nd ground distribution Systemtic plcement Keep ll pmos/nmos together Plce trnsistors in rows: shre source/drin diffusion Wiring on orthogonl metl lyers Assign preferred directions to M1 nd M2 Use diffusion only for devices, not for interconnect Use poly only for very locl interconnect ECE 261 Krish Chkrbrty 15 8
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