Development of Novel High Density System Integration Solutions in FOWLP Complex and Thin Wafer-Level SiP and Wafer-Level 3D Packages

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1 2017 IEEE 67th Electronic Components and Technology Conference Development of Novel High Density System Integration Solutions in FOWLP Complex and Thin Wafer-Level SiP and Wafer-Level 3D Packages André Cardoso, Leonor Dias, Elisabete Fernandes, Alberto Martins, Abel Janeiro, Paulo Cardoso, Hugo Barros NANIUM SA, Vila do Conde, Portugal Abstract Expanding FOWLP (Fan-Out Wafer-Level Packaging) from mainly 2D single or multi die solutions to 3D stacked multi-die solutions with SMDs integration, is of crucial importance to meet the requirements arising from new markets such as IoT/IoE and Wearables. This drives the development of new capabilities and technology breakthroughs in the current FOWLP process. e of the most hailed capabilities of FOWLP is the heterogeneous high-density system integration in a package. Wafer Level System-in-Package (WLSiP) already integrates active dies, passive components and even already-packaged components, in a wide range of geometries and materials. Vertical interconnections enable FO-based WL3D solutions, thru Package-on-Package (PoP) assembly. The nature of FOWLP, being a substrate-less technology and using thinfilm re-distribution layers, makes the package itself an active interposer. This concept allows very thin packages and PoP solutions, with excellent electrical and thermal behaviour compared to other packaging technologies. To accomplish the vertical package interconnect, or Thru Package Vias (TPV), required for package front to backside connections and 3D assembly, pre-formed vias solution was developed as the concept of choice at NANIUM for lower IO density and package body thickness from 200 to 400um. To allow the process on very thin Fan-Out wafers and, on the last stage, the double side RDL process to complete PoP solution, dedicated Temporary Wafer Bonding (TWB) and Debonding solution for FOWLP were developed and tested. This paper presents the approaches used to effectively enable FOWLP-based WLSIP and WL3D products: Preformed via solutions in three build-up options, from process development to reliability result; Wafer front-to-back RDL alignment solutions for high-accuracy 3D package; FOWLP TWB solution for WL3D/ PoP products; and stack-up/ stackdown solution for the final PoP implementation, when there is no space for additional die inside the WLSiP or due to the need to simplify routing complexity and reduce number of RDL s. Several demonstrators are built to demonstrate the above mentioned features, from a very thin, <300µm body, 12x12mm2 WLSiP with double side RDL for stack-up PoP, to a WL3D solution for a stack-down PoP. The work done is part of the collaborative European FP7-ICT project UNSETH Grant Agreement No. FP7-SECU ). (Unique Smart anti-tampering and Enveloping Technologies), performed together with a consortium of leading IDM, OEM, OSAT, material suppliers and academic/ institutes. Keywords Thin wafers; Fan-Out WLP; WLSiP; PoP, TWB I. INTRODUCTION Wafer Level Packaging (WLP) technologies have been evolving and extending capabilities towards Wafer Level 3D (WL3D) solutions. Fan-Out WLP (FOWLP) technology, in particular, has additionally extended and developed its heterogeneous integration capabilities towards Wafer Level System-In-Package (WLSiP), thus effectively allowing the merge of WLSiP and WL3D and offering unprecedented levels of packaging density. This constant development makes FOWLP technology particularly suitable for the continuous miniaturization seen and demanded in the mobile application market and in the upcoming IoT/IoE (Internet of things/internet of everything) applications, where a rapid growth is foreseen for the next years [1], Figure 1. Figure 1 Computing Cycle Evolution, Source: Morgan Stanley Research 2013 Figure 2 Global Internet Device Installed Base Forecast. SiP and 3D packaging plays a crucial role. Source: Strategic Analysis /17 $ IEEE DOI /ECTC

2 FOWLP is already one of the most promising packaging technologies, with a steep growth projection of 30% in the next years [2]. The extension to Fan Out WL3D, which stems from the design flexibility and system integration capability of FOWLP [3], will thus become of a great importance in the near future, by the ability to address the specific needs of the wearables applications and, in general, very thin and very dense 3D packages, as seen in Figure 2. Enabling FOWLP technology with this new and demanding specifications requires further developments in the packages architectures. As highlighted in the Yole Report Fan-Out and Embedded Die: Technologies & Market of February 2015 [2], from a first generation FOWLP based in Single/multiple Chip FOWLP solution to FO WLSiP and WL3D, there is a road to follow to achieve a full 3D PoP application. The OSAT industry offering FOWLP is thus aligned with this roadmap, Figure 3. The paper will focus mainly on the first two toolboxes, Vertical Interconnections, or TPV, and Temporary Wafer Bonding (TWB) for very thin FOWLP. Vertical Interconnection toolbox is crucial for high density solutions, by allowing both the package stack up and to explore the use of RDL on both sides of the package. Note that the use of TPV does not imply double-side RDL, as exemplified in Figure 4: the stacking up of packages can still be accomplished by TPV s and single-side RDL, in which the ends of the TPV opposite to the RDL serve directly as pads to receive the package above; is also a solution for the cases where the active side of the package must face up, while the pads/solder bumps connect to the PCB below (e.g., photonic applications, bio-medical applications) Figure 4 TPV applications examples, with both single and double side RDL Figure 3 Top: Fan-Out generations according to Yole [2]; Bottom: NANIUM s FOWLP integration roadmap To offer a full WLSiP/WL3D solutions, the FOWLP technology must extend its boundaries both by creating new toolboxes and by improving current capabilities. The following vectors have been identified: Vertical interconnection, i.e., Thru-Pkg-Vias (TPV), to allow double-side RDL and PoP assembly; Temporary Wafer Bonding and solutions, both for Very Thin Fan-Out wafer handling, below 300µm thickness, and to perform double-side RDL; Double Side RDL, 10µm L/S capability, with high accuracy top-to-bottom alignment; Embedding of low profile discrete SMD passives with high accuracy placement. TWB enables the handling of very thin wafers, below a practical self-sustaining thickness of <500µm (for 300mm wafer) and allows the execution of double-side RDL, i.e., protects one side while processing the other. TWB solutions for Si wafers exist in the market for years already, in very mature technology, however, given the very different nature of Fan-Out wafers (heterogeneous materials, varying CTE, low thermal conductivity), those TWB solution for Si wafers are not adequate. TWB solution for FOWLP have only been recently achieved for volume production by Nanium and EVG [4], yet with the goal for wafers within the µm thickness range. With the industry demand for thinner and thinner packages, processing Fan-Out wafers <300 µm is a must. Package thickness becomes even more critical for PoP constructions: for a stack of two Fan-Out packages to be kept <1mm, for example (Figure 4, top-left), the body of each package must be <300 µm. Such thin wafers bring shear fragility problems to TWB, therefore further developments are needed on the existing solution for FOWLP. The paper will show the results of TWB solutions for packages <250µm body thickness. For the two last points, the paper will also show the results of embedding 150 µm thin SMD s, in double side-rdl demonstrators, with TPV s. 15

3 II. DEMONSTRATORS DEFINITION A. SiP Package Dimensions Figure 5 Package and PoP outline dimensions C. RDL variants, Bottom and Top sides Figure 7 shows the four RDL variants of the SiP, built on a multi-project wafer. A two-layer RDL is implemented on the bottom side and a single-layer on the top side. The last RDL layer on the bottom side is a BGA with 400µm pitch. Designs A1 and A2, with 4 blocks of single-row TPV, implement the filling of top side with RDL daisy chain connected to TPV s and a large shielding area (lozenge in A1). Besides exemplifying a generic RDL on the top side connected to the bottom side with TPV s, these features demonstrate the ability to implement secure anti-tampering meshes and capacitive sensing/ shielding areas. Design C and E include 4 blocks of single-row TPV. Design C contains RDL features to assess L/S capability and Design E is dedicated to the PoP, with a 400µm pitch, 12x12 BGA receptacle. Figure 5 shows the outline dimensions for the Thin PoP demonstrator. The 12x12mm2 package is built on a 250µm thick Fan-Out wafer, aiming a total thickness of <0.5mm as a standalone package, including RDL stack and solder bumps, and <1.0mm thickness on a PoP configuration. For the PoP, a BGA receptacle matrix is implemented in the top side RDL, to receive a 5.5x5.5mm2 WLCSP package (a daisy-chain Si chip) with <0.5mm total thickness. The 12x12mm2, <250µm body is ~50:1 aspect ratio package, while at wafer level, 300mm diameter, it represents an AR of >1000:1. These are very challenging AR both for the wafer processing and for the package itself, in terms of wafer and package robustness and package reliability. Achieving a dual-side RDL SiP with such AR is a major challenge and highlight on this work. B. SiP components The demonstrator is a SiP, Figure 6, consisting of: Two daisy chain chips, 4x4mm2 and 2x2mm2 8 SMD, 0402, 150µm thickness (0-Ohm resistors) TPV blocks, 350µm pitch, single row (qty=4) and double row (qty=2), discussed in Section III Figure 6 Inside the package: SiP components, single row via blocks (left), double-row via blocks (right) Figure 7 RDL designs for 4 variants, A1, A2, C & E. PoP receptacle is visible on Design E, Top side RDL 16

4 III. THRU-PACKAGE VIAS (TPV) There are basically two ways to implement TPV s on the mold area of a Fan-Out package. Each method has its merits and disadvantages, briefly discussed in more detail below. A.) Drilling the mold on the required location by laser, for example, and metallizing the walls of these thruholes; this technique is also referred as Thru-Mold- Vias, TMV s; B.) Include Pre-Formed vias, or via blocks, prior to molding the reconstituted wafer, then exposing the top side of the vias by wafer grinding and laser ablation of the overmold. A. Laser Drilled TMV s The main advantage of laser drilled TMV s is the large flexibility for via placement and via quantity. I.e., one can place a single via or a randomly distributed group of vias in any place of the mold area. Another advantage is the minimal impact on the bill-of-material and on the supply chain, as no extra materials are required and it can be done at wafer level, in line with the RDL process. The disadvantages are dependency of pitch with the wafer thickness, the difficulty to laser drill on thicker wafers, but especially on the surface quality of the drilled holes, which bring electrical conductivity and reliability limitations if the metallization is done by sputtering and electroplating processes. The mold compound, being composed of SiO 2 fillers, with a large span of filler sizes, and gluing resin, responds non-homogenously to the laser drilling energy, creating a very rough surface. In turn, this roughness can create shadow areas to the sputtering, causing irregular electroplating, in top of the already irregular wall. This problem is depicted in Figure 8. Other disadvantages are the low throughput of laser drilling and the impact on cycle time of the additional via plating steps. Another potential disadvantage of the laser drilled TMV s is the need for RDL on both sides. Although this seems more of a consequence than a disadvantage, the method of Pre-formed vias described next dispenses the RDL process on the top side should this side includes only LGA or BGA pad. B. Pre-Formed Vias e disadvantage of Pre-formed vias is the limitation on random via placement and the need to group the vias into specific locations. At the limit, it is impractical to have single vias spread around the package. However, most designs allow the grouping of vias, which mitigates this limitation. Figure 9 Example of a Pre-Formed TMV s The pre formed vias rely on PCB-like technology to fabricate the substrate where via blocks are cut from. Thus, another disadvantage of pre-formed vias is the low density of vias and the pitch-thickness dependency borrowed from the PCB technology, in addition to the added complexity of design, bill of material and supply chain. Note that the design of via block substrate is added to package design set. However, the advantages of pre-formed vias overcome the disadvantages: Process simplicity a via block is regarded as any another component to be embedded in the SiP; Throughput one Pick&Place operation resolves a potentially large group of vias; furthermore, if a via block can be shared with the neighbor package within the wafer, the number of P&P operations can be halved; Direct Pad the substrate via design, one end of the vias can be terminated with large pad area, which, after exposure by grinding/laser ablation can directly act as LGA or BGA pad. This eliminates the need for a specific RDL layer for pad formation. This is not possible for laser drilled TMV s. Figure 8 Example of a laser drilled TMV, cross section As the via-blocks are molded over, the exposure the embedded end requires the removal of the mold above. This can be done directly by grinding, if grinding into the Cu pads is permitted, or by a combination of grinding and laser ablation. That is, the grinding of over-mold stops at a safe gap form the via pads, e.g., 20~50µm, whose gap is then removed by laser ablation. Via opening is an additional step, in line with the RDL process, but it cannot be regarded as disadvantage because any method to implement TPV s would necessarily imply additional steps. 17

5 C. Shared and Unshared TPV in SiP/PoP Demonstrator Given the pro-and-cons of TPV options discussed above, Pre-formed vias was the selected technology for TPV and were implemented in the demonstrators, with 350µm pitch. Moreover, the sharing of via blocks between packages, as a way to increase throughput, was exercised and evaluated. An implication of shared vias is that, after package singulation, the edge will expose the TPV block insulated material. The reliability of this solution is therefore evaluated. Figure 10 shows the use of shared and unshared TPV blocks among the variants. The single-row, unshared vias are implemented in variants A1/A2 and test the most demanding TPV at Pick&Place, with an Aspect ratio (AR) of ~10:1. The shared TPV blocks, implemented in variant C, is the least demanding at P&P, not only because it reduces the number of P&P operations, but also has the lowest AR, ~2.5:1. Figure 11 TWB of thin SiP wafer, with exposed Si. Any expansion mismatch between carrier and SiP wafer causes shear fractures at MC-die interface. Figure 10 Shared and Unshared TPV blocks. IV. TWB FOR VERY THIN FAN-OUT WAFERS A. Shear fracture suscetability of thin Fan-Out wafers The SiP wafer was originally over molded to >500µm, in order for the first RDL process, at Bottom-side, to be done as a self-sustaining wafer. To minimize warpage, such wafer required the embedded dies to be ~400µm thick. (A wafer with high asymmetry on Z-axis exhibits too much warpage). After completing RDL, the wafer is grinded to the final thickness, exposing the vias and the backside of the dies, as the final wafer is thinner than the dies itself. While this creates a highly symmetrical wafer, with minimal tendency to warp, it also minimizes the wall interface areas between dies and mold compound. The resulting wafer thus becomes too fragile to any shear stress caused by expansion mismatch between the wafer and carrier. This is shown in Figure 11. Further attempts using Fan-Out wafer as carriers, for a better CTE matching and lower shear forces, also failed, as shown in Figure 12. As the carrier thickness reduced, the shear fracture problem was transferred to the carrier. No sweet spot was found and this approach was abandoned. Figure 12 TWB of thin SiP wafer, with Fan-Out wafer carriers, for better CTE matching, but still with exposed Si. Figure 13 TWB solution for thin SiP wafer. The overmold increases wafer robustness but requires 2x TWB. 18

6 B. TWB solution for thin PoP wafers The solution found was to leave a significant overmold above the dies in the PoP wafer after grinding. The extra volume of mold compound and, especially, the existence of larger continuous areas of mold compound did increase the resistance of the PoP wafer to shear stress and the process on TWB was successful. In this solution, however, the dies have to be embedded already at final thickness, i.e., ~150µm to create a ~100µm overmold gap after grinding, and the wafer has to be molded at >300µm. The asymmetry on the Z-axis (~150µm on ~350 µm) creates intrinsically warped the wafer after mold. Therefore, this solution implied the use of TWB also for the first RDL process, with subsequent process cost impact. This is depicted in Figure 13. V. MANUFACTURING Some of the critical steps of, and the unique steps for the double-side RDL SiP are shown here. All other steps, like electroplating, e.g., are common to a standard process flow. A. Pick & Place (P&P) The uniqueness of SiP/PoP at P&P relates mainly to the TPV blocks and their Aspect Ratio. Figure 14 shows the component placement prior to molding, where is visible the large AR difference between the single-row, unshared TPV (~10:1) and the double-row, shared TPV (~2.5:1). The large AR required especial P&P tool and lower pick-up speed (from the dicing tape) to minimize the bending, which reduced the throughput. Conversly, the lower AR of the double-shared TPV brings the dual benefit of throughput (half the cycles at higher speed) and the use of standard P&P tools. In any case, with the proper parameters for each TPV type, no technical blocking point was observed at P&P. Figure 15 Top-Bottom RDL alignment solutions Both solution require few alignment dies in a wafer (e.g., two dies if a mask aligner) to be exposed by grinding, that is, dies must be thicker than the final grinding. These dies, being the thickest in the whole wafer, set the thickness at mold. Note that, being only few dies without overmold after grinding, the wafer resistance to shear stress at TWB is not compromised. Although both solutions are theoretically viable, the IR vision systems has the advantage of not requiring dedicated glass dies and in some cases, the product dies itself are enough for alignment, reducing the bill of material and construction complexity. Thus, only IR vison was tested and, given the successful results, glass dies were only used for microscope operator checking. The lithography equipment, by its turn, must allow a depth of focus (not depth of field) longer than the wafer thickness, so to focus on both sides of the wafer. C. TPV exposure via laser ablation. As discussed in III-B.), the exposure of the embedded side of TPV s can be done directly by grinding or by a combination of grinding and laser ablation. Direct grinding is the simplest method, but implies the ability of Cu grinding and adequate via design to cope with the grinding tolerance. That is, via pads to be exposed must be safely thicker than grinding coplanarity and Z precision. In case Cu grinding is not allowed due to contamination risks, the grinding can be taken to a safe gap from the pads and then laser ablation completes the exposure process. This approach was taken on this work and Figure 16 exemplifies the results. The entire TPV array was laser scanned, creating an ablated pool around the pad array. This method is faster than ablation pad-by-pad and more tolerant to small deviations. A standard laser mark equipment was used. Figure 14 P&P for the SiP demonstrators, showing the TPV blocks and a glass die for Top-Bottom RDL. B. Top-Bottom RDL alignment Two solution were devised for the Top-Bottom, high accuracy, RDL alignment: standard vision through glass dies, which were added to the wafer construction; Infrared vision through Si Dies, as Si is transparent to >1.2µm, Figure 15. Figure 16 TPV exposure by laser ablation of overmold 19

7 VI. RESULTS A. Manufacturing and assembly results Relevant manufacturing results are shown below: multiprojected SiP wafer; details of bottom side RDL and top side RDL on the four variants, including PoP (variant E); shared TPV diced at the edge and RDL L/S capability (variant C). Variant E, a 400µm CSP chip resulted in a PoP <800µm. Figure 19 Top side RDL on the four variants. Variant E is the PoP demonstrator, with a 400µm CSP chip assembled over. PoP assembly was done at board level: the SiP was 1 st assembled to the board, then the CSP mounted over the SiP, resulting on a PoP with total thickness <800µm! Figure 17 Double-side RDL multi-project wafer (left) and detail of glass die for RDL alignment check (right) Figure 20 Variant C details: 10/10µm L/S capability on the top-side RDL; exposed shared TPV block at pkg edge. Figure 18 Details of Ball (Bottom) side 2-layer RDL, showing the RDL connection to the TPV (top), the 400µm pitch BGA (center), connection to Daisy Chain die (bottom left), and embedded SMD (bottom right) B. Reliability results All variants of Thin SiP/PoP were submitted to package reliability and board reliability, according to Table 1 below. 20

8 Table 1 Reliability test matrix Component Level Reliability Precon HTS uhast TC500 TC h+ 500h 150ºC MSL1 96h+96h 130ºC, 85%rh 500x 2c/h -40/125C A1/A2 Skip 192h C - shared TPV E - PoP 192h 500x 2c/h -40/125C Not applicable, PoP assembled at board level Board level TCoB 500 TCoB 1000 Drop Test 500x 500x >DT30 1c/h 1c/h JEDEC std -40/125C -40/125C 0 fails 0 fails 0 fails Precon: Bake 125ºC, 24h; Soak 85ºC, 85%RH, 168h; Reflow of 3 cycles, Tmax 260ºC. (JESD22-A113, MSL1 JSTD020D-01.) At the editing of this paper, some reliability tests were ongoing. The interim results already show the feasibility and reliability of the shared and unshared TPV, a main feature for PoP/3DSiP. No delaminations nor degradations were detected on the interface of TPV to either mold compound or RDL layers (Figure 21) and shared TPV did not show any fracture or interface problems to the mold compound at the exposed edges (Figure 22). At board level, TCoB500 and DT passed. VII. CONCLUSIONS With the aim of increasing FOWLP packaging density, several solutions for Very Thin WLSiP and 3D/PoP were successfully tested and demonstrated in a 12x12mm 2 SiP, 250µm body thickness, with double-side RDL, assembled in a stand-alone SiP and PoP configuration. The highlights of this work can be summarized as: Successful implementation of TWB solution for FO wafers with 250µm thickness; Successful test of TPV block as vertical interconnect solution, and further validation of shared TPV blocks for manufacturability and throughput improvement; Successful assembly of a PoP with <800µm profile, with a 400µm CSP chip soldered on the Thin SiP top RDL; Successful embedding of 150µm profile SMD and test of high density 10µm L/S with high accuracy top-bottom side RDL alignment. ACKNOWLEDGMENT The authors would like to express their thanks to the European Commission for their funding of the UNSETH project, (Unique Smart anti-tampering and Enveloping Technologies), Grant Agreement No. FP7-SECU Figure 21 Cross section details after several reliability tests. No failures observed on TPV s, at its interface to RDL and mold compound. No problems on embedded SMDs. Figure 22 Variant C, exposed shared TPV block at pkg edge. No fracture, fissure or interface problems to the mold compound, retaining hermetic sealing after stress tests. REFERENCES [1] John H. Lau (ASM Pacific Technologies Ltd.), Semiconductors and packaging for the Internet of Things, Chip Scale Review Magazine, edition May-June 2015, pp [2] Azémar, J., Fan-out and embedded die: Technology and Market, Yole Développement report, [3] Steffen Kroehnert, José Campos, André Cardoso, Eoin O Toole, Abel Janeiro, Nuno Vieira, FOWLP Technology ewlb Enabler for Packaging of IoT/IoE Modules, IMAPS 48 th Annual International Symposium on Microelectronics, Orlando, October 2015 [4] Cardoso A., Pires M., O Toole E., Pinto R., Kröhnert S., Uhrmann T., Burggraf J., Wiesbauer H., Temporary Wafer Carrier Solutions for thin FOWLP and ewlb-based PoP, International Wafer Level Package Conference, San Jose, California, October [5] Jérome Azémer, Phil Garrou (YOLE Dévelopment) Fan-out packaging: what can explain such a great potential?, Chip Scale Review Magazine, edition May-June 2015, pp 5-8 [6] Hamid Eslampour, SeongWon Park, HanGil Shin, JaeHan Chung, YoungChul Kim (STATS ChipPAC), Advancements in package-onpackage (PoP) technology for next-generation smartphone processors, Chip Scale Review Magazine, edition March-April 2014, pp [7] Jin, Y., Baraton, X., Yoon, S. W., Lin, Y., and Marimuthu, P. C., "Next Generation EWLB (embedded Wafer Level BGA) Packaging." 12th Electronics Packaging Technology Conference (2010) 21