Memory Innovation Made Possible by Suppliers
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1 Memory Innovation Made Possible by Suppliers Er-Xuan Ping Managing Director, Applied Materials September 9, 2016 External Use
2 Current e-nvm Status and Challenges Outline STT-MRAM, ReRAM, PCRAM as New e-nvm Applied Materials New e-nvm Development Conclusions 2
3 Current e-nvm Status and Challenges Outline STT-MRAM, ReRAM, PCRAM as New e-nvm Applied Materials New e-nvm Development Conclusions
4 e-nvm in Microcontroller (MCU) Access Speed Endurance CPU/ Register Cache - SRAM Memory SRAM Retention (non- volatility) Density Code Storage - eflash (NOR) Volatile & Non Volatile Memory on the Same Chip Infineon TC1784, 90nm (180 MHz, 2.5 MByte Flash) 4
5 Markets and Applications 5
6 Technology Status CMOS vs. e-flash Flash Summit 2013, Spansion Do Dormans et al, NVSMW Year/Gen Source: Yole, 2015 Renesas Announced 28nm Technology (with MONOS cell) 14nm Flash Summit 2013, Spansion 3 rd Generation Super Flash SST, 32th European SSDVC
7 MCU Scaling Issues Cost F 2 R. Strenz, IEDM 2011 Performance Power Consumption Y. Thachev, and A. Kotov, Proc. ESSDERC, 2006 Reliability High Temp Retention A. Kotov, Leti Innovation Days Memory Workshop
8 Current e-nvm Status and Challenges Outline STT-MRAM, ReRAM, PCRAM as New e-nvm Applied Materials New e-nvm Development Conclusions 8
9 New NVM Entrants PCRAM NOR NVM ReRAM e-nvm STT-MRAM DDR Toshiba/SanDisk, ISSCC 2013 Micron/Sony, ISSCC 2014 High Density Fast NVM 9
10 New Memory Attributes NVM Read Latency NVM Write Latency Source: Kosuke Suzuki, Steven Swanson, University of California, San Diego technical report CS , May Faster Than Flash 10
11 Cost Advantage of New e-nvm in MCU Current MCU Chip SRAM, Logic FETs NOR Flash Source Gate Drain Source Drain FEOL One Mask 10+ Mask Adder 3 Mask Adders Memory (STT MRAM) BEOL Logic FET IBM, ECS Trans STT-MRAM MCU Chip FEOL Source: Macronix, Applied Physics A,
12 PCRAM Integration Process Flow Passivation Patterning Cell Stack Oxide Polish Oxide Fill PECVD/PEALD Liner Treatment Inspection Post Etch Clean Cell Material Etch HM Open Lithography High Selective HM Dep Top Electrode Dep Phase Change Material Dep Polish Bottom Electrode H.Horii et al, Symp on VLSI Tech 2003 CMOS As PCRAM cell pitch reduces and architecture changes to 3D XPoint, HAR processes needed. 12
13 ReRAM Integration Process Flow Passivation Patterning Cell Stack Oxide Polish Oxide Fill PECVD/PEALD Liner Treatment Inspection Post Etch Clean Cell Material Etch HM Open Lithography High Selective HM Dep Top Electrode Dep ReRAM Stack Dep Polish Bottom Electrode CMOS Panasonic/IMEC, VLSI 2015 Current ReRAM faces variability, endurance issues. Forming circuit is extremely important. 13
14 Current e-nvm Status and Challenges Outline STT-MRAM, ReRAM, PCRAM as New e-nvm Applied Materials New e-nvm Development Conclusions 14
15 Low Temperature High Quality Dielectrics For BEOL Integration Flowable CVD Dielectrics (Surface chemical reaction leads to good film quality) Source: Applied Materials Experimental Data 15
16 ALD Dielectrics and Metals For HAR Structure Integration Mean Stack Film Thickness (A) Mean Thickness = 24.2Å WtW Uniformity = 0.53%, 1σ 1σ WiW Uniformity = 0.71%, 1σ 1σ TPT = WPH Thickness WiW Uniformity HfO WiW Uniformity (%) ,000 4,000 6,000 8,000 10,000 Wafer Count Intensity (counts) 600 TiN TiN Theta ( ) Source: Applied Materials Experimental Data 16
17 Endura PVD Technology For STT-MRAM Film Stack Precision Magnetic Film and MgO Dielectric 17
18 Material Engineering TaOx By O Implant In Ta Metal Source: Applied Materials Experimental Data 18
19 Cell ETCH and PEALD Dielectric For Novel Material Integration Solution Typical Requirements Flat HM No visible metal re-dep Minimize damage >85 side wall In-situ Encapsulation Hard Mask Open Critical Material ETCH Reactive Ion Etch Dual Ribbon Beam Dry Clean PEALD Liner (Low Temp < 250 C) Source: Panasonic/IMEC, VLSI
20 Sym3 Etch Control Byproducts + + Plasma Low conductance leads to accumulation and resulting etch variation Simulation result Cathode Byprod. Conc. (a.u.) Plasma High conductance produces uniform etch Pump Sym3 Chamber High conductance Designed for efficient byproduct removal 0 20
21 Minimizing Within-Die Variation: Loading Control Multiple Patterning Induced CD Variation Loading Challenge Sym3 Performance 20nm Tunable Radical / Ion flux Ratio with Pulsing and High Conductance Required for Micro and Depth Loading Control Source: Applied Materials Experimental Data 21
22 Centura STT-MRAM Etch System For Non-Volatile Magnetic Material Etch Solution Source: Applied Materials Experimental Data 22
23 Current e-nvm Status and Challenges Outline STT-MRAM, ReRAM, PCRAM as New e-nvm Applied Materials New e-nvm Development Conclusions 23
24 Summary Flash based e-nvm scaling faces scaling challenges CMOS scaling outpaced e-nvm cell scaling. Transition to new cell technology is needed to align with advanced CMOS technology Non-charged based STT-MRAM, PCRAM, ReRAM memory cells are compatible with advanced high K/MG CMOS and they are suitable for e-nvm scaling. Implementation of new cell technology depends on e-nvm product requirements for the market and manufacturing cost Applied Materials is very actively working in the STT-MRAM, PCRAM and ReRAM technologies 24
25
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