MEMS Fabrication Technology Training May Wang, QST Corp

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1 MEMS Fabrication Technology Training May Wang, QST Corp 2015/05/12

2 Outlines: Unique challenges in the MEMS fabrication technologies Key process modules in MEMS device fabrication Overview of mainstream MEMS/CMOS integration schemes Correlation between MEMS design and key process modules The future of MEMS ECO-System

3 Unique challenges in the MEMS fabrication technologies

4 Traditional IC Vs.MEMS Electrical vs. Mechanical+ MEMS devices usually involve multidisciplinary systems such as magnetic, optical, thermal, biochemical and etc. When scaling down, need to consider the overall impact. As most MEMS systems are multidisciplinary (e.g. fluidic, magnetic, mechanical and etc), the scaling properties of any of these components can limit the overall scaling of the system. Devices modeling/or CAD tools are partially matured. It usually requires several iterations to optimize the design using certain process flow. Si vs. Other Materials Materials with magnetic property are not compatible with IC foundry and stringent measures need to be implemented to avoid cross-contamination Any introduction of new materials will need supporting infrastructure and usually long lead time for evaluation and implementation Planar 2D vs. 3D The need to fabricate submicron geometry on aggressive topography (could range from couple of micron to > The etch process need to cover high aspect ratio features, usually >100:1, and over great depth (~10-100um)

5 Traditional IC Vs.MEMS Special Equipment/Chemistry Equipment used to deposit/etch the specific materials (such as Ge, Ta and etc) are not commonly used in IC foundry; other equipment is specific for MEMS fabrication such as bonder and double-side aligner Chemistry might not compatible (for example, KOH for Si wet etch) Standard vs. Function specific packaging MEMS types of packaging are more complex than most standard IC packages because they require a System-in-Package type of assembly. Additionally, MEMS packages usually have very specific requirements like a module with a cavity, a hole in the substrate, an optical window for optical MEMS, or full vacuum hermeticity at the die level. 95% vs % Process Standardization Standard and compatible process/ip available for fabless design house Non- or limited-standardization at best. Diversity of devices and rapid adoption of some early products encourages the one product, one process model ; Large players of the MEMS field still on traditional IDM model Mainstream MEMS foundry/idm on <=6 wafer format provide no compelling reason to standardize key process modules/equipment types

6 Commonly used processes in MEMS device fabrication

7 Mechanical Properties of Silicon Crystalline silicon is a rigid and brittle material that deforms elastically until it reaches its yield strength. No elastic deformation for Silicon. Tensile yield strength = 7 GPa (~1500 lb suspended from 1mm²) Young s Modulus near that of stainless steel: {100} = 130 Gpa, {110} = 169 Gpa, {111} = 188 Gpa Mechanical properties uniform, no intrinsic stress Mechanical integrity up to C Good thermal conductor, low thermal expansion coefficient High piezoresistivity (ideal candidate material for pressure sensor)

8 Key Process Modules: Bulk machining and Surface Micromachining Wet etch Dry Etch - Ion Mill and DRIE Wafer Bonding Sacrificial Layer and release

9 Silicon Crystallography

10 Surface Micromachining Leave wafer substrate untouched, but add/remove additional layers of materials on the surface Uses the similar process philosophy as IC fabrication More cost-effective fabrication technique but usually require expensive equipment Use sacrificial materials When sacrificial material is removed, only structural materials are left to form the functional devices

11 Silicon Bulk Micromachining Involves removing materials from the crystalline silicon substrate directly Traditional MEMS fabrication technique; compatibility issue with IC process Typically use wet etch process (isotropic and anisotropic), with device constructed using etch stop plane DRIE process is used to create small geometry More expensive technique but with low capital equipment investment

12 Wet etch - Isotropic Etching of Silicon HNA: hydrofluoric acid (HF), nitric acid (HNO3) and acetic (CH3COOH) or water HNO3 oxidizes Si to SiO2 HF converts SiO2 to soluble H2SiF6 Acetic prevents dissociation of HNO3 Etch masks SiO2 etched at nm/min Non-etching Au or Si3N4

Wet Etch - Anisotropic Etching of Si Etching of Si with KOH Si + 2OH - Si(OH) 2 2+ + 4e - 4H 2 O + 4e - 4(OH) - + 2H 2 Crystal orientation etch rate ration: {110}:{100}:{111} = 600:400:1 Angle

13 Wet Etch - Anisotropic Etching of Si Etching of Si with KOH Si + 2OH - Si(OH) e - 4H 2 O + 4e - 4(OH) - + 2H 2 Crystal orientation etch rate ration: {110}:{100}:{111} = 600:400:1 Angle between {110}:{111} = o TMAH, tetramethyl ammonium hydroxide, wt.% (90 o C) Etch rate (100) = μm/min, 3X slower than KOH Al safe, IC compatible Etch ratio (100)/(111) = Etch masks: SiO2, Si3N4 ~ nm/min Boron doped as etch stop, up to 40X slower

14 Anisotropic Etching of Silicon II Convex corners bounded by {111} planes could be attacked and etched away eventually

10 20 cm-3 reduces KOH etch rate by 20-100 times Gas or solid phase boron diffusion Beams, suspended

15 Boron-Doped Etch Stop Control etch depth with boron doping (p++) At high dopant level, injected electrons recombine with holes in valence band and are unavailable for reactions to give OH- [B] > cm-3 reduces KOH etch rate by times Gas or solid phase boron diffusion Beams, suspended films (such as diaphragm in pressure sensor) 1-20 μm layers possible Buried p++ compatible with CMOS process

Physical Dry Etch Ion Milling: Reduced pressure environment (<50 mtorr) to Increases mean free path between molecules Inert gas injected at low pressure is used as milling species RF Plasma in

16 Physical Dry Etch Ion Milling: Reduced pressure environment (<50 mtorr) to Increases mean free path between molecules Inert gas injected at low pressure is used as milling species RF Plasma in chamber Energy transfer to gas molecules creates a plasma of equal numbers of ions and molecules Positive ions bombard negatively charged target (wafer), removing molecules from the surface Key Characteristics: Could sputter away variety of materials; Good choice when finding the right etch chemistry for certain materials becomes an issue Low selectivity in most of the cases; low etch rate; no sidewall passivation so profile is difficult to control

DRIE (Deep Reactive Ion Etch) Bosch process 2 steps with fast switch in-between: etching (SF6 as etch chemistry) passivation(c4f8 as passivation gas) Key advantages

17 DRIE (Deep Reactive Ion Etch) Bosch process 2 steps with fast switch in-between: etching (SF6 as etch chemistry) passivation(c4f8 as passivation gas) Key advantages Anisotropic with vertical sidewall profile High etch selectivity over etch mask, such as PR, SiO2, metal and etc. High aspect ratio Sub-micron feature sizes possible

18 DRIE Process Parameters and trend Source Power (Ws): RF Power (13.56MHz) applied to initiate & maintain the plasma for de-association Pressure (p): Pressure in the reactor chamber Bias Power (Wb): Power applied to the chuck, usually in low frequency Gas pulse: Flow and duration for etch, deposition (and polymer removal phases) Distance: Distance between the source and wafer chuck General parameter trends: Ws : Etch rate, Polymer removal rate & deposition rate P : Etch rate, polymer deposition rate Wb : Etch rate, Selectivity Distance : Etch rate, Selectivity

Bosch Process Variation In the standard Bosch process, polymer is removed b SF 5+. In etching high aspect ration features, it can leads to improper removal polymer bottom layer.

19 Bosch Process Variation In the standard Bosch process, polymer is removed b SF 5+. In etching high aspect ration features, it can leads to improper removal polymer bottom layer. The ability of O 2 plasma to remove polymer is ~5 times of SF 5+. The recipe will need to adjusted accordingly to balance the etch rate, selectivity, sidewall profile and etc.

Types of wafer bonding techniques Complicated MEMS device requires not only the micromachining of individual components, but also the assembly

20 Types of wafer bonding techniques Complicated MEMS device requires not only the micromachining of individual components, but also the assembly of components to form a complete set through wafer bonding. Bonding technique is also an essential for creating wafer level hermetic packaging

Anodic bonding (I) Anodic bonding is a chemical bonding process that joins together a bare silicon wafer and a sodium-containing glass substrate, for example, Corning Pyrex 7740 Fundamental packaging

21 Anodic bonding (I) Anodic bonding is a chemical bonding process that joins together a bare silicon wafer and a sodium-containing glass substrate, for example, Corning Pyrex 7740 Fundamental packaging technique to the manufacture of sensor/device which requires transparent cover and/or hermetic environment Bonding performed at o C in a vacuum, air or inert gas High voltage is necessary ( V) and so not CMOS wafer compatible

22 Anodic bonding principle(ii) Mechanisms Positive ion migration (Na+) in glass away from Si-glass interface towards the cathode The electrostatic attraction hold the two substrate Chemical bonding of glass to silicon Current = 0, indicating bonding is complete Key points: Has to maintain bare Si surface as the bonding interface, a very thin layer of SiO2 on the Si wafer is sufficient to disturb the current flow and the bond Thermal expansion match is preferable, for example, Corning 7740 is 3.2 x 10-6/ o C and silicon wafer is 2.6 x 10-6/oC

23 Fusion bonding Si direct bonding Generally Pre-CMOS as the requirement of high temperature anneal. Clean/particle-free surface is the most important factor for void free bonding and the surface should be smooth(rq<1nm). Wafer flatness is very crucial (<25um for 8 wafer) The final bond strength increases with the anneal temperature. At temperatures between 800 o C and 1200 o C the intrinsic strength of bulk silicon is reached.

24 Bonding Strength Strong correlation between bonding strength and anneal temperature: T<300 o C, exhibits relatively constant bond strength equal to the bond strength of the wafers prior to anneal. 300 o C<T<800 o C, the bond strength increases and then levels out. It is presumed that an Si O Si bridging bond is formed between the surfaces and a water molecule is liberated. T>800 o C, the bond strength begins to increase again. In this third region, it has been suggested that surfaces can more easily deform (oxide flow) and trapped water may oxidize surfaces, bringing them into better contact. T>1000 o C, the bond strength is in the range of the strength of the silicon crystal itself. Thermally sensitive devices can be bonded with a sufficient strength for wafer dicing at temperatures between 200 o C and 400 o C by using chemical surface activation methods.

25 Measurement of bonding strength Commonly used method including shear strength and Maszara blade method Where E is the Young's modulus of wafers, t w, t b are the thickness of wafer and blade L is the length of crack generated RT bonding strength Bonding Strength Comparison

26 Eutectic Bonding Principle Wafer bonding technique with an intermediate metal layer that can produce a eutectic system. Those eutectic metals are alloys that transform directly from solid to liquid state, or vice versa from liquid to solid state, at a specific composition and temperature without passing a two-phase equilibrium, i.e. liquid and solid state. The eutectic temperature can be much lower than the melting temperature of the two or more pure elements. Popular eutectic bonding system include: Al-Si, Al-Ge, AlCu-Ge, Au- Si, Au-Sn, Au-In and Cu-Sn Eutectic bonding could be used to create hermetic seal and also electrical contact in one process.

27 Eutectic bonding (Ge/Al) Compatible with CMOS foundry Low eutectic temperature feasible for CMOS/MEMS monolithic integration Forms ohmic contact with heavydoped Si surface Squeeze out control critical for device yield and reliability Uniformity of pressure and temperature is crucial for optimum bonding quality

28 Use of Sacrificial Layer (a) Sacrificial Layer deposition (b) Patterning of layer (c) Metal Deposition (d) Etch of sacrificial layer to free Deposit first sacrificial Deposit and pattern first poly Deposit and pattern second sacrificial Pattern contacts Deposit and pattern 2 nd poly Etch sacrificial

y Poly-Silicon XeF2 Aluminum Photoresist Oxygen plasma

29 Sacrificial material systems Structure Sacrificial Etchant Poly-Silicon Silicon dioxide HF SiO 2 / Si x N y Poly-Silicon XeF2 Aluminum Photoresist Oxygen plasma Photoresist Aluminum Al etch Aluminum Silicon EDP,TMAH,XeF2

30 Vapor HF release Courtesy of SPTS

31 General VHF process trend Lower temperature processes give better selectivity; Material variation, such as SiN type, will affect the selectivity greatly Oxide etch rates increase at lower temperatures for given HFpp There is a trade off between selectivity and possible negative effects of high oxide etch rates

32 Overview of mainstream MEMS and CMOS integration schemes

MEMS/CMOS integration method SIP / Hybrid Monolithic

Wafer-level interconnect Parasitics More Less Size

Necessary Packaging Complexity Simple/Reliable

33 MEMS/CMOS integration method SIP / Hybrid Monolithic IMEC SIP / Hybrid Monolithic Connection Wire Bond Wafer-level interconnect Parasitics More Less Size Usually bulky Compact IC-Fab compatible Not required Necessary Packaging Complexity Simple/Reliable Parallel Tech Development Yes No Development Cycle Shorter Longer

doped poly-si layer (for electrical interconnect and ground plane. Sacrificial oxide is sandwiched between each poly-si level.

34 Sandia (MEMS-First)/CMOS Platform CMOS Device Area MEMS Device Area SUMMiT V (Sandia Ultra-planar Multi-level MEMS Technology V) 1.0 micron, 5-level, surface micromachining (SMM) technology featuring four layers of poly-si (mechanical structure) fabricated above a highly doped poly-si layer (for electrical interconnect and ground plane. Sacrificial oxide is sandwiched between each poly-si level. The sacrificial SiO 2 film defines the amount of mechanical play in hinges. optional metal layer can be applied to the top poly-si layer for electrical connections

35 SUMMiT V Structure Diagram

36 ST THELMA Process Thick Epitaxial Layer for Micro-Gyroscopes and Accelerometers Yan Lock, ST Micro, 2013 Semicon

Litho & Etch Anchor/Ground Litho/Etch Sacrificial oxide etch SiC removal Epi Poly Growth &

37 ST THELMA Process Flow Thermal Oxidation Poly-Si Deposition & Doping Mask Poly Litho & Etch Poly-Si oxidation Metal Sputtering/Litho & Etch SiC Deposition Sacrificial Oxide Dep Trench Litho & Etch Anchor/Ground Litho/Etch Sacrificial oxide etch SiC removal Epi Poly Growth & Doping Epi Poly planarization Yan Lock, ST Micro, 2013 Semicon Sensor/Cap wafer alignment Wafer boding

IMEC MEMS/CMOS Platform Combines PECVD and CVD at 2 Torr, high-quality films can be obtained at low temperature (450 o C) with very high deposition rates (~100nm/min).

45 mcm, a tensile stress of 35 MPa and a very low strain gradient of 3.

38 IMEC MEMS/CMOS Platform Combines PECVD and CVD at 2 Torr, high-quality films can be obtained at low temperature (450 o C) with very high deposition rates (~100nm/min). This is the IMEC process for the deposition of thick SiGe layers (e.g. for capacitive sensing applications) on top of standard CMOS. A low resistivity of 1.45 mcm, a tensile stress of 35 MPa and a very low strain gradient of 3.6E10-6 um-1 have been achieved using a top Si-rich stress compensation layer The contact between Al and SiGe was found to be ohmic as required for MEMS/ CMOS integration Cross-section of the PECVD/CVD poly-sige multilayer Schematic cross-section of the integrated gyroscope.

encapsulation) is silicon wafer with etched

39 X-Fab MEMS Platform (I) SOI wafer based technology Sensor elements formed by Silicon DRIE process Releasing of movable parts using isotropic etch Top cap wafer (for encapsulation) is silicon wafer with etched cavity 6 inch platform Discreet CMOS and MEMS

sensing in Z- direction Low inside cavity pressure

40 X-Fab MEMS Platform (II) Cost effective wafer level packaging by wafer bonding Recessed fingers enable sensing in Z- direction Low inside cavity pressure Metal connections to the movable sensor structures

InvenSense CMOS/MEMS flow (I) The engineered silicon on insulator (ESOI) wafer is formed using a standard silicon handle wafer with simple etched targets for backside alignment

The MEMS wafer is completed by etching the device layer to form standoffs (mask 3) that define the seal ring and electrical contacts to CMOS; depositing and patterning a germanium

41 InvenSense CMOS/MEMS flow (I) The engineered silicon on insulator (ESOI) wafer is formed using a standard silicon handle wafer with simple etched targets for backside alignment (mask 1); followed by oxidation and cavity etch (mask 2). A second wafer is fusion bonded to the handle wafer and subsequently thinned to define the device layer thickness. The MEMS wafer is completed by etching the device layer to form standoffs (mask 3) that define the seal ring and electrical contacts to CMOS; depositing and patterning a germanium layer (mask 4) over standoffs; and patterning (mask 5) and deep reactive ion etching the device layer to form the mechanical structure. By Steven Nasiri, Martin Lim, and Mike Housholde, InvenSense

42 InvenSense CMOS/MEMS flow A standard CMOS wafer fabricated by an independent foundry and a cavity (mask 6) is etched into CMOS wafer to provide clearance for moving MEMS structures. The MEMS wafer is bonded to the CMOS wafer using AlGe eutectic bonding between the Al on the CMOS and the Ge on the MEMS wafer. After bonding, a portion of the MEMS wafer is removed by conventional tab saws to expose the CMOS wire bond pads.

43 InvenSense Device Image (I)

44 InvenSense Device Image (II) One platform to integrate two major inertial sensors: accelorometer and Yole, technical presentation

45 Correlation between MEMS design and key process modules performance and yield

46 Key Considerations Performance Sensitivity Linearity Noise Band Width Manufacturability Process variation Key module uniformity Reliability Stiction Harsh environment

47 Example - Q Factor vs. Pressure Dotted line: Squeeze-file damping Dashed line: Stoke s damping Solid line: Total air damping The ability to achieve high vacuum within the cavity and keep it hermetic, is the key to produce high performance gyroscope (high Q value)

Quadrature error y yz yz Z y z y z y z y z y z y z k k k

48 Example - DRIE etch key parameter Impact of profile angle on device performance & yield Q-factor (comb driving) Quadrature error y yz yz Z y z y z y z y z y z y z k k k k k k k k k k k k k k k k K cos sin 2 2 sin 2 cos 2 2 2

mechanical cross coupling of 2%. This can hardly be detected by SEM.

49 Impact of Sidewall Profile Simulations show that an asymmetric flexure angle of 0.05 and profile asymmetries of 10 nm of the outer spring results in an unacceptable mechanical cross coupling of 2%. This can hardly be detected by SEM. If the anisoelasticity coefficient equals 1%, becomes equal to /s for a 10-kHz gyroscope 15% yield 90% yield

50 DRIE Common Process Issues Depth: 8.6um Depth: 27.3um Pattern loading Effect Sloped sidewall profile Large Scallop Size Edge tilt Si grass formation Notching

Micro-loading Effect Feature with different CD and aspect ratio will have different etch rate, which is a physical phenomena related to the etchant availability at microscopic level Large open area

51 Micro-loading Effect Feature with different CD and aspect ratio will have different etch rate, which is a physical phenomena related to the etchant availability at microscopic level Large open area of Si are locally over-consuming fluorine radicals, which then leads to surrounding features affected with slower etch rate Design will need to take this into consideration and unify the gap CD size during structure release to minimize the impact of such phenomena

Backside damage control with EDP Over-etch is necessary to cover the etch

device backside Effective point will help to identify the punch-through point during

flow and design layout has to be adjusted to enable better and effective endpoint

52 Backside damage control with EDP Over-etch is necessary to cover the etch non-uniformity and u-loading effect; But too much over-etch will induce damage on device backside Effective point will help to identify the punch-through point during the process release and help to control the over-etch percentage Film stack, process flow and design layout has to be adjusted to enable better and effective endpoint detection. >20% OE EP signal of 17% change with <1% open ratio ~10% OE EP signal of 35% change with ~19% open ratio

53 Example - Fusion Bonding Alignment of device layer to bottom cavity substrate through open frame. The AM on the bottom cavity wafers could give clear signal for alignment check SAM (Fusion Bonding) Consistent fusion bonding / thinning result. Top Si (device layer) could be thinned to 25um with <2um TTV

Killer defect Si grass Causes: Contamination from mask and/or chamber

Re-deposition of mask materials Impact: If the Si-grass happens in the

will create large void during fusion bonding and thus result total

If happens during structure release process, it will generate particle

54 Killer defect Si grass Causes: Contamination from mask and/or chamber walls (due to polymerization) Native oxide or particle micro-mask Re-deposition of mask materials Impact: If the Si-grass happens in the early stage of the process (for example, before fusion bonding), it will create large void during fusion bonding and thus result total yield loss. If happens during structure release process, it will generate particle which could interface with mechanical movement of the device. In the worst case, it will effect local void in Eutectic bonding process which

55 Process impact on device performance Fusion bonding to obtain device layer on top of cavity substrate Eutectic bonding to form electrical connection between device layer and CMOS as well as hematic encapsulation Sample Device Schematics Eutectic bonding layer thickness variation Z-gap Z-axis sensitivity Eutectic bonding squeeze out reliability and yield Stress Offset Pressure / Vacuum Q-factor Sensitivity & Noise & Power

56 Dependence on process (I)

57 Dependence on process (II) Process variation: effect on sensitivity +/-20% vertical gap 2.5x sensitivity variation +/- 0.3 um beam width 1.5x sensitivity variation High variation requires ASIC complexity to trim Stiction: related to contact surface properties, is a major MEMS failure mode Bonding quality: determines device mechanical stability and also packaging hermeticity; in some case, electrical connectivity is also related to bonding quality Misalignment: margin built in layout, affects device size and also device zero offset

58 Issues Specific to MEMS - Packaging MEMS nature is micromechanical structure: Some form of encapsulation is necessary to avoid damaged during wafer dicing process Package environment is important for some device that hermeticity is required Special packaging requirement such as transparent cover, hole in the package for pressure sensor and etc Main considerations: Bonding method Stack thickness Mechanical stress of package Coefficient of thermal expansion mismatch Thermal management Electrical feed through method Foot print

59 The Future of MEMS ECO-System

60 The Future of MEMS ECO-SYSTEM (I) Monolithic CMOS/MEMS process platform further standardization (for at least certain type of devices such inertial sensors and combos) to yield device with lower parasitic, better performance and lower power consumption 8 inch wafer become main stream to leverage IC infrastructure for cost effectiveness. Process design kits (PDKs) and MPW format similar to those in traditional IC industry will improve the efficiency of MEMS-IC co-design and also time-tomarket. Design and modeling software company to cooperate with foundry/idm, providing more accurate prediction of device functionality based on specific process flow characteristics.

61 The Future of MEMS ECO-SYSTEM (II) Wafer level encapsulation and packaging technology will also become mainstream to enable higher/stable packaging yield, smaller MEMS device footprint, and cost-effective wafer-level sensor combo. Wafer Level Chip Scale Package using Through-Silicon-Via provide higher levels of system integration, which ultimately speeds up time-to-market, will also be adopted to further lower the sensor foot print. THE END

L5: Micromachining processes 1/7 01/22/02

97.577 L5: Micromachining processes 1/7 01/22/02 5: Micromachining technology Top-down approaches to building large (relative to an atom or even a transistor) structures. 5.1 Bulk Micromachining A bulk