Micromachining: What you really need to know

Transcription

1 Micromachining: What you really need to know Presented to Proficience #33 class in Jan.-May term of 2005 Lecture 2 G. K. Ananthasuresh suresh@mecheng.iisc.ernet.in Mechanical Engineering Indian Institute of Science Bangalore, INDIA

2 2 Microfabrication methods Surface micromachining Bulk micromachining Wafer-bonding Others Micro-moulding Deep reactive ion etching Laser/ion assisted micromachining Soft-lithography Unconventional methods

3 3 Surface micromachining Deposit or grow silicon dioxide Silicon wafer Pattern the oxide using a mask Deposit polysilicon Pattern polysilicon Sacrifice oxide layer by dissolving The sacrificial layer process to make released structures (Berkeley)

4 4 Types of etching Isotropic etching in HNA With agitation Without agitation Anisotropic etching in KOH (111) plane (111) (100) silicon (110) silicon Slanted surfaces

5 5 Bulk micromachining Etch using a mask Silicon wafer Boron doping using a mask Flip and bond to a glass Glass Dissolve undoped silicon in EDP Boron doped dissolved wafer process (Michigan)

6 6 Wafer bonding Etch a cavity in a wafer Bond another wafer Thin down / polish and etch Released cantilever using MIT s wafer bonding process

7 7 Making an electrostatic micromotor using surface micromachining Side view Top view After sacrificing oxide layers Rotor Stator poles Cronos MUMPs (formerly MCNC MUMPs)

8 8 Making a micromotor Deposit poly0 Etch poly0 Deposit oxide1 Dimples in oxide1 Etch oxide1 Deposit poly1

9 9 Making a micromotor (contd.) Etch poly1 Deposit oxide2 Cross-section up to this point Cronos MUMPs (formerly MCNC MUMPs)

10 10 Making the micromotor (contd.) Etch oxide2 Deposit poly2 Etch poly2 Deposit and etch metal Cronos MUMPs (formerly MCNC MUMPs) Cross-section before sacrificing oxide layers

11 11 Finished micromotor

12 12 Micromotor after release Cronos MUMPs (formerly MCNC MUMPs)

13 13 How much should we know about u-fab? Being able to draw the process flow diagrams from a description. Visualizing a process from a crosssection.

14 14 Visualize device from a verbal description of the process Being able to draw the process flow diagrams from a description. Shallow pits were etched into n-type substrates, and p-type deflection electrodes were diffused in the above pits, followed by fusion bonding of a second wafer above the first. The top wafer was then ground and polished down to a thickness of 6 um. A passivation layer was then formed on the top wafer and sensing piezoesistors were formed using ion implantation, after which contact holes for metallization to connect to the diffused deflection electrodes were etched. Bond pads and interconnect metallization were then deposited and patterned, followed by etching of the diaphragm from the back of the wafer. Finally, two slots were etched next to the beam to release it over the buried cavity. (Petersen et al., 1991)

15 15 Process flow Wire bond

16 16 Making elements of mechanisms A surface micromachined hinge (Kris Pister, Berkeley) Substrate hinge

17 17 Raising off the substrate Lin et al., 1995; Proc. IEEE MEMS workshop.

18 18 Floating hinges Mask layout

19 19 SCREAM process Noel MacDonald, Cornell university Deposit and pattern mask oxide Etch bottom sidewall oxide Deep RIE silicon etch Second deep RIE silicon etch Deposit sidewall oxide Isotropic silicon etch

20 20 Basic materials used in microfabrication Silicon and its compounds Single-crystal silicon (SCS) Polycrystalline silicon (poly) Silicon dioxide (oxide) Silicon nitride (nitride) Silicon carbide Metals Aluminium, gold, copper, silver, nickel, etc. Glass Pyrex, sapphire, quartz, etc. Ceramics Mostly used in packaging in multi-chip modules Polymers Coming into vogue, mostly in biomems applications

21 21 Basic process steps Photolithography Oxidation Thin-film deposition Selective etching through a mask Wafer bonding Doping Epitaxial growth Thick-film deposition Dicing, die-bonding, and wire-bonding

22 22 Photolithography for patterning a mask layer Photoresist layer (spincast and baked)) Mask layer 1 Layer to be selectively etched UV light Photo-lithography mask 2 After developing the photoresist 3 After etching the mask layer 4 After stripping off the photoresist 5

23 23 Silicon crystal lattice 8 atoms at vertices 6 atoms at face-centers 4 along body-diagonals at 1/4 th distance from the vertices Diamond lattice Each silicon atoms holds hands with four neighbors via covalent bonds. Source: unknown

24 24 Flats on wafers

25 25 (100) wafers

26 26 Orifice etched in (100) wafer with KOH

27 27 Vertical sidewalls with KOH-etching of (100) wafers

28 28 (110) Wafers with KOH etching

29 29 Mobile electrons and holes in silicon lattice Source: unknown

30 30 Oxidation If the oxide layer s thickness is t ox, Net increase in wafer thickness is 0.54t ox. B.E. Deal and A.S. Grove, "General Relationship for the Thermal Oxidation of Silicon", J. Appl. Phys. 36, 12, 3770 (1965) Si + 2H O SiO + H Si + O SiO 2 2 Wet Dry 1/2 A ( t+ τ ) xox () t = 1+ 4B A * ( x0 + Ax0) A= 2 D + ; B = 2 DC / N; τ = ks h B Deal and Grove model LOCOS in recessed silicon Local Oxidation of Silicon (LOCOS) Bird s beaks

31 31 Thin-film deposition techniques Chemical vapour deposition (CVD) LPCVD PECVD Physical vapour deposition (PVD) Vacuum evaporation Sputtering Epitaxy VPE, LPE, MPE Electroplating Electroless plating Spincasting

32 32 Doping with donors and acceptors V(or 15)-group (Phosphorous, Arsenic, etc.) have five valence electrons. They donate one electron and permanently become positive ions. This electron roams around and helps increase conductivity. III(or 13)-group (Boron, Gallium, etc.) have three valence electrons. They accept one electron and permanently become negative ions. This leads to a mobile hole. Source: unknown

33 33 Etching Wet Isotropic Anisotropic Electrochemical Lift-off patterning Dry Plasma etching: Reactive ion etching (RIE) Deep RIE (DRIE) Vapour phase dry etching Lift-off deposition

34 34 DRIE Developed and patented by Bosch (Germany). It is time-multiplexed deep etching (TMDE). Mask: oxide Etchant: SF 6 Substrate: silicon Protective coat: C 4 F 8 Scalloping effect

35 35 DRIE-spring Klaassen, E. H., et al. "Silicon Fusion Bonding and Deep Reactive Ion Etching; A New Technology for Microstructures," Digest of Technical Papers from Transducers '95/Eurosensors IX, Vol. 1, June 25-29, 1995, Stockholm, Sweden, pp

36 36 Lift-off deposition/patterning Desired patterning of the layer to be deposited It is like using a stencil (or screen printing) Spincast and pattern photoresist Evaporate (deposit) the layer Lift-off unwanted deposition along with the photoresist

37 37 Wafer bonding Wafer-to-wafer bonding Anodic Fusion Adhesive Eutectic

38 38 Planarization Why do we need planarization? MUMPs process with three structural layers The geometry and topography of the latter layers get increasingly more complicated. Leads to the problem of stringers (loose pieces upon release) too. Planarization Chemical mechanical polishing Resist-etchback Polymer-filling

39 39 The need for planarization step in MEMS Cronos MUMPs process with three structural layers The geometry and topography of the latter layers get increasingly more complicated. Leads to the problem of stringers (loose pieces upon release) too.

40 40 HARM processes High Aspect Ratio Micromachining (HARM) Useful for most devices and essential for some Good out-of-plane stiffness LIGA HEXSIL

41 41 LIGA LIGA: German acronym for lithography, electroplating, and moulding Developed by Karlsruhe Nuclear Research center in late 1980 s. Figure: courtesy of Sandia National Laboratory

42 42 Sandia s LIGA product A heat exchanger that had overall dimensions of 1.7 x 2.3 inches designed by Lockheed Martin Missles and Space. The feature sizes were as small as 23µm and the finished product was vacuum tight.

43 43 HEXSIL A polysilcion template-based moulding process (Keller and Ferrari, 1994) Deposition of a sacrificial layer (SiO 2 ) Silicon mould with careful plasma etch CVD deposition of polysilicon Lapping and polishing of poly Deposition and patterning of another poly layer Micro parts Release

44 44 Other ( unconventional ) processes Soft-lithography (embossing) Precision machining Micro-EDM (electro-discharge machining) Abrasive cutting Laser micromachining Ion milling, focused ion beam (FIB) milling Micro stereo lithography Ink-jet type deposition FIB deposition Laser-assisted CVD Etc.

45 45 Soft lithography A new high-resolution lithography using an elastomeric stamping mould. George Whitesides, Harvard PDMS Polydemethylsiloxane Making the PDMS mould

46 46 How was micro-accelorometer made in 1979? Bulk micro machined Piezoresistor -based sensing Roylance L.M., Angell J.B. A batch fabricated silicon accelerometer IEEE Trans. on Electron Devices 26, (1979)

47 47 Verbalize the process steps from a device cross section Verbalizing a process from a cross-section and then visualizing it geometrically. A micro-diaphragm pressure sensor (Sugiyama et al., 1986) Top view Aluminium Silicon nitride Polysilicon N-type (100) Si What process was used to make this? (IEEE Int. Electron Devices Meeting, 1986, pp )

48 48 Visualizing a process flow Deposit a nitride layer using LPCVD Deposit another nitride layer Etch the nitride layer to leave a square window Etch nitride layers Deposit polysilicon using LPCVD Etch polysilicon and silicon using KOH Deposit a thick nitride layer Deposit Al using vacuum evaporation and pattern Deposit polysilicon piezoresistors Seal using a nitride layer using plasma CVD

49 49 Order of the process steps is important! We should not etch the pyramidal pit first. This is because the subsequent layers conform to the pit s surface and it will not be possible to get a membrane.

50 50 A surface micromachining process

51 51 SUMMiT V Sandia Ultra-planar Multi-layer Micromachining Technology Oxide4 CMP Oxide3 CMP Nitride (0.8 um) Oxide2 Oxide1 Thermal oxide (0.63 um) Poly0 A gear train on a moving platform. Figures: courtesy of Sandia National Laboratory

52 52 An example of a surface-micromachined device Micro parallel manipulator with three degrees of freedom made using polysilcon. fabricated using an external foundry (MUMPs).

53 53 A bulk micromachining process

54 PennSOIL 54 (Univ. of Pennsylvania Silicon-On-Insulator Layer process) Bulk micromachining process based on Silicon on Insulator (SOI) wafers A single releasable structural layer with selectively doped regions Doped Silicon Silicon SiO 2 Moulton and Ananthasuresh, Sensors and Actuators A, 90 (2001), pp

55 55 PennSOIL (contd.) Four inch wafers are diced into pieces for use in 2 equipment A membrane is formed out of the thin layer of the SOI wafer by a KOH etch from the back of the wafer

56 56 PennSOIL (contd.) An intermediate nonstructural silicon etch must be done for front-back alignment Selective doping is accomplished by applying dopant material on top of an oxide mask

57 57 PennSOIL (contd.) The dopant is driven in at high temperature in the furnace Devices are formed by etching through the silicon membrane. This is done with a plasma etch and NiChrome mask.

58 58 Devices made with PennSOIL (a bulk process) Doped Silicon SiO 2 Silicon Linear actuator Three dof platform Single actuator 1 mm

59 59 A wafer-bonding process

60 60 A wafer-bonding based shake-and-make compliant micro device A' E D C B A Made using MIT s waferbonding process (Schmidt s group, MIT) Saitou and Jakiela; Ananthasuresh (1995)

61 61 MIT microengine MIT Microengine (Source: Epstein, 2003) Several wafers patterned with deep features are bonded together.

62 62 Serial (non-batch) micromachining processes

63 63 Excimer laser micromachined devices Aluminum ETC micro gripper micromachined using KrF 248 nm excimer laser A stainless steel ETC actuator Li and Ananthasuresh, Micromechanics and Microengineering, 12 (2002), pp

64 64 FIB milling Focused ion beam can be used to deposit as well as etch. Features of the size tens of nanometers can be obtained. Usually used in chip-repair. An ultra-sensitive acceleometer Moore et al., Cambridge University

65 65 FIB-milled linkage FIB-milled straight-line linkage at K. U. Leuven. (Ananthasuresh and Puers, 2003)

66 66 More FIB s structures (Reyntjens and Puers, 2001)

67 67 A meso -scale process

68 68 LTCC (green tape) technology Low Temperature Co-fired Ceramic tapes Developed by Du Pont for microelectronic packaging. Also called green tapes

69 69 Why LTCC tapes? Easily Machinable: In the green state, ceramic tape are soft, pliable, and easily machinable. The material facilitates easy fabrication of mesoscopic features (100 µm 10 mm). In the fired state, features can be machined using diamond tools, abrasive jets, and lasers. Tailored properties: It is possible to cast tapes of various ceramic compositions to obtain desirable properties. Laminated 3-D structures: Large number of layers can be laminated to form 3-D structures. Easy integration of electronics: A well developed thick film technology facilitates the deposition of various metals and electrical components on the tapes in the green state and the formation of threedimensional interconnects. Hybrid structures: It is possible to fabricate hybrid structures consisting of ceramics, glass, polyimides.

70 70 LTCC tapes for integrated microfluidics A thick-film technology Registration hole Channel/Cavity Resistor Processing steps Pattern tapes Via Screen-print conductors, resistors, etc. Ceramic tape Collate and laminate. Conductor (Bau, Santiago, and Ananthasuresh) Co-fire.

71 71 Patterning; shrinkage Before firing After firing Shrinkage of about 12% in plane, and 15% out-of-plane.

72 72 Meso-scale, magnetically actuated pump with one diaphragm (Kim, Ananthasuresh, and Bau)

73 73 Process flow for the LTCC-Kapton pump Ceramic Tape Chamber Inlet hole Process flow STEP 1 Positive photoresist Copper Chromium tiecoat Kapton (a) Outlet hole (b) Chromium tiecoat Copper Positive photoresist STEP 2 A STEP 2 Mask UV light Cross section A-A Positive photoresist Copper Chromium tiecoat Kapton A B STEP 3 (c) Chromium tiecoat Copper Positive photoresist STEP 3 Copper Chromium tiecoat Via Chromium tiecoat Copper Kapton valve Cross-section B-B STEP 4 The pressure chamber was fabricated with low temperature co-fired ceramic tapes. Rapid prototyping Layered manufacturing B (d) (Kim, 2002) STEP 5 Via Kapton Copper electromagnetic coils