Interconnect Dr. Lynn Fuller Webpage:

Transcription

1 ROCHESTER INSTITUTE OF TECHNOLOGY MICROELECTRONIC ENGINEERING Interconnect Dr. Lynn Fuller Webpage: 82 Lomb Memorial Drive Rochester, NY Department webpage: Interconnect.ppt Page 1

2 ADOBE PRESENTER This PowerPoint module has been published using Adobe Presenter. Please click on the Notes tab in the left panel to read the instructors comments for each slide. Manually advance the slide by clicking on the play arrow or pressing the page down key. Page 2

3 OUTLINE Introduction Interconnect Resistance Interconnect Capacitance RC Delays Lumped and Distributed Calculations Buffers Inductance Antenna Electromigration Packaging Board Level Interconnect References Page 3

4 INTRODUCTION This document will discuss on chip interconnects and a brief introduction to chip packaging and board interconnect. Front End - Back End - Well Formation Isolation Technology Transistor Formation Local Interconnect and Contacts Multilayer Metal and Passivation Packaging Board Level Interconnect Page 4

5 INDUSTRY ROADMAP Polysilicon CD µm Contact/Via CD µm Min Interconnect CD µm Metal height/width aspect ratio 1.5:1 2:1 2.5:1 3:1 3.5:1 4:1 Number of metal levels DRAM Microprocessor Interconnection Length m ,000 Reliability FITs/meter Cost $/cm 2 /level mile = 1625 meters Page 5

6 PROPERTIES OF SELECTED METALS Aluminum Copper Gold Tungsten Chrome Nickel Solder Electrical Resistivity mohm -cm Plasma Etch? Yes-Cl No No Yes-F No No - Solder? No Yes No No No Yes - Page 6

7 PROPERTIES OF ALUMINUM CONDUCTORS Advantages: High Electrical Resistivity, r (bulk) = 2.7 µohm-cm Good ohmic Contact to n+ and p+ Silicon (~40 ohms for 0.5µm) Easy to Deposit Good Adherence to SiO2 and Si Easy to Pattern Easy to Wire Bond To Low Cost Limitations: Low temperature Reaction with Silicon Spiking Low Electromigration Hillock Growth Dry Etching uses Chlorine Chemistry No suitable CVD process Step Coverage is Poor in High Aspect Ratio Contacts/Vias Page 7

8 0.5 µm THREE LEVEL METAL PROCESS NO CMP M3 Tungsten Plugs M2 LTO SOG TiN M1 n+ n+ Silicon 1995 Page 8

9 SIX LAYER ALUMINUM, W PLUGS, CMP, DAMASCENE OF LOCAL W INERCONNECT Six levels aluminum interconnect with tungsten plugs, CMP, and damascene of local tungsten interconnect for 0.18 µm gates. Can you identify the transistors? 2000 Page 9

10 CMP Page 10

11 Transistors MOORE S LAW The number of transistors per chip doubles every 18 months, at no cost to customers.* The industry has kept pace with Moore s Law: Transistors keep getting smaller Transistors keep getting closer together Transistors keep getting faster The result of these trends: Year Real estate on a chip is very expensive. A chip can no longer be built like a printed circuit board with wires (metal pattern) taking up most of the chip area. The patterned metal layers are placed above the chip and separated by insulators. This is called a multilevel interconnect system ? Ser Page 11

12 WESTECH CMP TOOL CMP- Chemical Mechanical Planarization (wafer polishing to achieve flat planar surface). Essential for multi-level interconnect. Page 12

13 CMP DAMASCENE PROCESS LTO Pattern Trenches in Oxide Fill with Copper Metal Metals that can not be plasma etched can be defined by etching oxide (LTO), depositing metal and CMP CMP Excess Metal Off Page 13

14 DUAL DAMASCENE PROCESS Prior Metal Layer + LTO Pattern and Etch Contact to Prior Metal Pattern and Etch Trench for Conductor Deposit Copper CMP excess Metal off Page 14

15 6 LAYER COPPER INTERCONNECT Copper Layer 6 Copper resistivity ~1.7 µohm cm Copper Layer 5 Copper Layer 4 Copper Layer 3 Copper Layer 2 Copper Layer 1 Local tungsten interconnect at 0.2 µm transistor gates Page 15

16 COPPER INTERCONNECT Page 16

17 MULTILAYER METAL, W PLUGS, CMP Layers Metal Page 17

18 LOW-K FOR INTERCONNECT Page 18

19 ELECTRICAL CONSIDERATIONS Resistance Contact Resistance Capacitance Interlevel Dielectric (low k = low er) Lumped Interconnect Delay Distributed RC Delay Calculations Buffers Clock Distribution Power Distribution Page 19

20 ELECTRICAL CONSIDERATIONS Delay (ps) Gate Delay Interconnect Delay Technology Node (nm) Delay is related to the time required to change a voltage on a capacitance, RC time constant or CV/I for constant current Page 20

21 THE THIN FILM RESISTOR R = Rho L / Area = Rhos L/W R (ohms) Rho (ohm-cm) Rhos (ohms/square) w t Rho is the bulk resistivity of the material (ohm-cm) Rhos is the sheet resistance (ohm/sq) = Rho / t L R Area Note: sheet resistance is convenient to use when the resistors are made of thin sheet of material, like in integrated circuits. Page 21

22 CALCULATION OF RESISTANCE FOR METAL LINES Page 22

23 RESISTANCE OF A LONG WIRE Example: 0.13um, 8 layer copper, layers um thick, layers um thick Rhos = ohm/sq for layers 1-6 Rhos = ohm/sq for layers 7-8 For length of 1000um and width of 100nm R = 109 ohms/mm for layers 1-6 R = 54.5 ohms/mm for layers 7-8 Page 23

24 CAPACITANCE OF A LONG ALUMINUM WIRE Capacitance to a ground plane (simple) Coupling capacitance to parallel wires Page 24

25 CAPACITORS Capacitor - a two terminal device whose current is proportional to the time rate of change of the applied voltage; I = C dv/dt a capacitor C is constructed of any two conductors separated by an insulator. The capacitance of such a structure is: C = eo er Area/d d where eo is the permitivitty of free space Area er is the relative permitivitty Area is the overlap area of the two conductor separated by distance d eo = 8.85E-14 F/cm er air = 1 er SiO 2 = 3.9 C I + V - Page 25

26 INTERCONNECT CAPACITANCE CALCULATIONS 26.9fF Page 26

27 CMOS INVERTER SHOWING CAPACITANCE During switching one transistor is off while the other is in saturation. The self capacitance is the capacitance connected to the output. One C D-sub and the overlap capacitance from gate to drain for each transistor. The capacitance from gate to drain is a Miller capacitance and is Cm =C D-sub VIN In this example: Cself = 2x(24.3fF + 1.8fF) Cself=2x25.2fF=50.4fF CG is everything connected to Vin Including miller effect CG=25.6fF 9.2fF C Gin 9.2fF C Gin 1.8fF C G-S C G-D 1.8fF 1.8fF C G-D C G-S 1.8fF VDD C D-Sub 24.3fF VOUT 24.3fF C D-Sub Page 27

28 INTERNAL CAPACITANCE CALCULATION All the internal capacitances can be calculated from the equation, C=eoer Area/d, where d is the oxide thickness or width of the space charge layer. This spreadsheet does the calculations for the capacitors shown on the previous page. The total internal capacitance for the inverter with this technology is ~1.15pF ~1.15pF Page 28

29 INTERNAL CAPACITANCE CALCULATION ~0.238fF ~0.238fF Page 29

30 CURRENT FOR 2um and 250nm NMOS 2um NMOS 3.3V = ~750uA 750uA 3.3V 360uA 1.5V 100nm NMOS 1.5V = ~360uA Page 30

31 ESTIMATED GATE DELAY FOR 2um and 250nm CMOS ~ td = CV/I = RC where V=Vdd/2 C and I from previous pages For 2um technology V=1.65 volts, C=1.15 pf, I=750uA td = 1.15p 1.65 / 750u = 2.53ns For 100nm technology V=0.75 volts, C=0.238 ff, I=360uA td = 0.238f 0.75 / 360u = 0.496ps Compare with Interconnect delay of RC for wiring 1000um long RC = 1800 ohm 26.9fF = 48ps Interconnect delay is 100xGate Delay Page 31

32 LUMPED MODEL OF LONG WIRE R R R R R + - C C C C C Distributed RC line as a lumped RC ladder R Distributed RC line C Page 32

33 SIULATION RESULTS FOR LUMPED AND DISTRIBUTED Page 33

34 BUFFERS If gate delay is small compared to interconnect delay then adding buffers can help reduce the overall delay. R Buffer R R R R + - C C C C C Page 34

35 BUFFERS If gate delay is small compared to interconnect delay then adding buffers can help reduce the overall delay. See simulation below: pending. Page 35

36 OTHER CONSIDERATIONS Antenna effects, coupling capacitance, more Busses Multi Core RF on chip interconnects Optical on chip interconnects Clock distribution Power and ground Page 36

37 SUMMARY FOR INTERCONNECT Technology has already passed the point where interconnect delay equals gate delay. Today the transistors are so small and fast that the individual gate delay is small compared to on chip interconnect delay. Page 37

38 INTRODUCTION FOR PACKAGING The chips are packaged to protect them from damage and to facilitate interconnection with other chips (board level interconnect) Page 38

39 TERMINOLOGY AND ACRONYMS BGA - Ball Grid Array PBGA - Plastic Ball Grid Array (or PLGA Plastic Land Grid Array) PGA - Pin Grid Array SOT - Small Outline Package TSOT - Thin Small Outline Package TCP - Tape Carrier Package (or COT - Chip on Tape) DIP - Dual In-line Package (PDIP - Plastic DIP) CERDIP - Ceramic DIP, Ceramic Side Brazed DIP QFP - Quad Flat Package (MM - Multilayered, Bumpered, HD (High Density) Page 39

40 PACKAGE TYPES CLCC - Ceramic Leadless Chip Carrier CQFP - Ceramic Quad Flat Pack PQFP - Plastic Quad Flat Pack SIP - Single In-line Package MCM - Multi-Chip Module CSP - Chip Scale Packages (refers to size of package ~ size of chip) DIP - (Shrink DIP, CSIP, PDIP, Skinny DIP) SIP - Single In-line MCM - Multichip Module PGA - Pin Grid Array Ball Grid Array (PBGA, SOP - Small Outline Package (Gull-leaded, J-leaded, TSOP) Flat Pack (Quad Flat Pack, Plastic QFP, Ceramic) Leadless Chip Carrier Leaded chip Carrier Tape Automated Bonding Page 40

41 CHIP TO PACKAGE CONNECTION Wire Bonds Solder Bumps Connectors Press-fit Zero Insertion Force Aluminum Wire Bonds Solder Bumps Page 41

42 WIREBOND INTERCONNECT TO PCB Wire Bonding Movies Page 42

43 WIREBONDS Stacked memory chips wire bonded in parallel to Data Bus. Page 43

44 THROUGH WAFER VIAS Page 44

45 SOLDER PAD ARRAY Page 45

46 BALL GRID ARRAY PBGA-1 PBGA-2 Page 46

47 SOLDER BALLS Alpha Metals 500,000 Spheres 63%Sn/37%Pb gms Page 47

48 BALL GRID ARRAY Balls are placed on the chip by a machine. The sphere placer is the tool used to place the solder spheres onto the substrate technologies (ball grid array). The spheres are lead and tin, usually with a little silver (referred to as eutectic). There are no-lead solder spheres and other spheres that have different compositions. In the past hi-lead (90% lead, 10% tin) was used. The spheres are anywhere from 12mil to 30mil in size. One specific tool (Vanguard 5020) is the premier tool in the industry. It works by gravity placement. Flux is placed on the product (which is held in a fixture with vacuum) by screen printing. On the same equipment with a simple rotation of the main fixture the spheres are placed using a stencil. The solder spheres roll into the stencil and then are dropped onto the spots on the part where flux has now been placed. It's phenomenal, the equipment can place upwards of 10,000 spheres in 60seconds or less! Page 48

49 C4 SOLDER BUMPS Controlled-Collapse Chip Connections (C4) The C4 process typically is based on aluminum die pad with sputtered nickelcopper or evaporated chromium-copper and electroless nickel for the Under Bump Metal layers. The bumps themselves are created in a large number of ways. High-melting (~300 C) solders, often with high lead content, which when melted form a bump from the inherent surface tension of solder. Page 49

50 C4 FLIP CHIP Flip chip has the highest density of interconnects. Example: P2SC single-chip RISC 6000 processor has 2050 C4 bumps on 18x18 mm. Page 50

51 C4 SOLDER BUMP STRUCTURE Final Metal Pad Die Passivation Solder Bump Under Bump Metallurgy Silicon Wafer The final metal pad is typically Aluminum or Copper. If Aluminum the under bump metal might be Nickel on Chrome on Aluminum solder will not stick to Aluminum but will stick to Nickel, Nickel will not stick to Aluminum but will stick to Chrome, Chrome will stick to Aluminum. (other materials and alloys are also used) Page 51

52 C4 SOLDER BUMP FORMATION 1. Silicon wafer with aluminum metal pad and passivation. 2. Under Bump Metallurgy of Cr/Ni/Cu is sputtered. 3. Pattern and Etch to form under bump metal cap. 4. Screen print solder paste and reflow to form bump. Page 52

53 After Reflow C4 SOLDER BUMP FORMATION After Printing Close Up of Bump Page 53

54 SUMMARY FOR PACKAGING AND CHIP LEVEL INTERCONNECT There are many types of packages and chip level interconnect. Engineers are creating new innovative ways to squeeze more into a smaller space regularly. Page 54

55 REFERENCES 1. Analysis and Design of Digital Integrated Circuits, 3 rd Edition, David A. Hodges, Horace G. Jackson, Resve A. Saleh 2. Others Page 55

56 HOMEWORK 1. None 2. more Page 56